amlogic,meson-g12a-reset.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
  2. /*
  3. * Copyright (c) 2019 BayLibre, SAS.
  4. * Author: Jerome Brunet <jbrunet@baylibre.com>
  5. *
  6. */
  7. #ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
  8. #define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
  9. /* RESET0 */
  10. #define RESET_HIU 0
  11. /* 1 */
  12. #define RESET_DOS 2
  13. /* 3-4 */
  14. #define RESET_VIU 5
  15. #define RESET_AFIFO 6
  16. #define RESET_VID_PLL_DIV 7
  17. /* 8-9 */
  18. #define RESET_VENC 10
  19. #define RESET_ASSIST 11
  20. #define RESET_PCIE_CTRL_A 12
  21. #define RESET_VCBUS 13
  22. #define RESET_PCIE_PHY 14
  23. #define RESET_PCIE_APB 15
  24. #define RESET_GIC 16
  25. #define RESET_CAPB3_DECODE 17
  26. /* 18 */
  27. #define RESET_HDMITX_CAPB3 19
  28. #define RESET_DVALIN_CAPB3 20
  29. #define RESET_DOS_CAPB3 21
  30. /* 22 */
  31. #define RESET_CBUS_CAPB3 23
  32. #define RESET_AHB_CNTL 24
  33. #define RESET_AHB_DATA 25
  34. #define RESET_VCBUS_CLK81 26
  35. /* 27-31 */
  36. /* RESET1 */
  37. /* 32 */
  38. #define RESET_DEMUX 33
  39. #define RESET_USB 34
  40. #define RESET_DDR 35
  41. /* 36 */
  42. #define RESET_BT656 37
  43. #define RESET_AHB_SRAM 38
  44. /* 39 */
  45. #define RESET_PARSER 40
  46. /* 41 */
  47. #define RESET_ISA 42
  48. #define RESET_ETHERNET 43
  49. #define RESET_SD_EMMC_A 44
  50. #define RESET_SD_EMMC_B 45
  51. #define RESET_SD_EMMC_C 46
  52. /* 47 */
  53. #define RESET_USB_PHY20 48
  54. #define RESET_USB_PHY21 49
  55. /* 50-60 */
  56. #define RESET_AUDIO_CODEC 61
  57. /* 62-63 */
  58. /* RESET2 */
  59. /* 64 */
  60. #define RESET_AUDIO 65
  61. #define RESET_HDMITX_PHY 66
  62. /* 67 */
  63. #define RESET_MIPI_DSI_HOST 68
  64. #define RESET_ALOCKER 69
  65. #define RESET_GE2D 70
  66. #define RESET_PARSER_REG 71
  67. #define RESET_PARSER_FETCH 72
  68. #define RESET_CTL 73
  69. #define RESET_PARSER_TOP 74
  70. /* 75-77 */
  71. #define RESET_DVALIN 78
  72. #define RESET_HDMITX 79
  73. /* 80-95 */
  74. /* RESET3 */
  75. /* 96-95 */
  76. #define RESET_DEMUX_TOP 105
  77. #define RESET_DEMUX_DES_PL 106
  78. #define RESET_DEMUX_S2P_0 107
  79. #define RESET_DEMUX_S2P_1 108
  80. #define RESET_DEMUX_0 109
  81. #define RESET_DEMUX_1 110
  82. #define RESET_DEMUX_2 111
  83. /* 112-127 */
  84. /* RESET4 */
  85. /* 128-129 */
  86. #define RESET_MIPI_DSI_PHY 130
  87. /* 131-132 */
  88. #define RESET_RDMA 133
  89. #define RESET_VENCI 134
  90. #define RESET_VENCP 135
  91. /* 136 */
  92. #define RESET_VDAC 137
  93. /* 138-139 */
  94. #define RESET_VDI6 140
  95. #define RESET_VENCL 141
  96. #define RESET_I2C_M1 142
  97. #define RESET_I2C_M2 143
  98. /* 144-159 */
  99. /* RESET5 */
  100. /* 160-191 */
  101. /* RESET6 */
  102. #define RESET_GEN 192
  103. #define RESET_SPICC0 193
  104. #define RESET_SC 194
  105. #define RESET_SANA_3 195
  106. #define RESET_I2C_M0 196
  107. #define RESET_TS_PLL 197
  108. #define RESET_SPICC1 198
  109. #define RESET_STREAM 199
  110. #define RESET_TS_CPU 200
  111. #define RESET_UART0 201
  112. #define RESET_UART1_2 202
  113. #define RESET_ASYNC0 203
  114. #define RESET_ASYNC1 204
  115. #define RESET_SPIFC0 205
  116. #define RESET_I2C_M3 206
  117. /* 207-223 */
  118. /* RESET7 */
  119. #define RESET_USB_DDR_0 224
  120. #define RESET_USB_DDR_1 225
  121. #define RESET_USB_DDR_2 226
  122. #define RESET_USB_DDR_3 227
  123. #define RESET_TS_GPU 228
  124. #define RESET_DEVICE_MMC_ARB 229
  125. #define RESET_DVALIN_DMC_PIPL 230
  126. #define RESET_VID_LOCK 231
  127. #define RESET_NIC_DMC_PIPL 232
  128. #define RESET_DMC_VPU_PIPL 233
  129. #define RESET_GE2D_DMC_PIPL 234
  130. #define RESET_HCODEC_DMC_PIPL 235
  131. #define RESET_WAVE420_DMC_PIPL 236
  132. #define RESET_HEVCF_DMC_PIPL 237
  133. /* 238-255 */
  134. #endif