amlogic,meson-axg-reset.h 2.8 KB

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  1. /*
  2. *
  3. * Copyright (c) 2016 BayLibre, SAS.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. *
  6. * Copyright (c) 2017 Amlogic, inc.
  7. * Author: Yixun Lan <yixun.lan@amlogic.com>
  8. *
  9. * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
  10. */
  11. #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
  12. #define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
  13. /* RESET0 */
  14. #define RESET_HIU 0
  15. #define RESET_PCIE_A 1
  16. #define RESET_PCIE_B 2
  17. #define RESET_DDR_TOP 3
  18. /* 4 */
  19. #define RESET_VIU 5
  20. #define RESET_PCIE_PHY 6
  21. #define RESET_PCIE_APB 7
  22. /* 8 */
  23. /* 9 */
  24. #define RESET_VENC 10
  25. #define RESET_ASSIST 11
  26. /* 12 */
  27. #define RESET_VCBUS 13
  28. /* 14 */
  29. /* 15 */
  30. #define RESET_GIC 16
  31. #define RESET_CAPB3_DECODE 17
  32. /* 18-21 */
  33. #define RESET_SYS_CPU_CAPB3 22
  34. #define RESET_CBUS_CAPB3 23
  35. #define RESET_AHB_CNTL 24
  36. #define RESET_AHB_DATA 25
  37. #define RESET_VCBUS_CLK81 26
  38. #define RESET_MMC 27
  39. /* 28-31 */
  40. /* RESET1 */
  41. /* 32 */
  42. /* 33 */
  43. #define RESET_USB_OTG 34
  44. #define RESET_DDR 35
  45. #define RESET_AO_RESET 36
  46. /* 37 */
  47. #define RESET_AHB_SRAM 38
  48. /* 39 */
  49. /* 40 */
  50. #define RESET_DMA 41
  51. #define RESET_ISA 42
  52. #define RESET_ETHERNET 43
  53. /* 44 */
  54. #define RESET_SD_EMMC_B 45
  55. #define RESET_SD_EMMC_C 46
  56. #define RESET_ROM_BOOT 47
  57. #define RESET_SYS_CPU_0 48
  58. #define RESET_SYS_CPU_1 49
  59. #define RESET_SYS_CPU_2 50
  60. #define RESET_SYS_CPU_3 51
  61. #define RESET_SYS_CPU_CORE_0 52
  62. #define RESET_SYS_CPU_CORE_1 53
  63. #define RESET_SYS_CPU_CORE_2 54
  64. #define RESET_SYS_CPU_CORE_3 55
  65. #define RESET_SYS_PLL_DIV 56
  66. #define RESET_SYS_CPU_AXI 57
  67. #define RESET_SYS_CPU_L2 58
  68. #define RESET_SYS_CPU_P 59
  69. #define RESET_SYS_CPU_MBIST 60
  70. /* 61-63 */
  71. /* RESET2 */
  72. /* 64 */
  73. /* 65 */
  74. #define RESET_AUDIO 66
  75. /* 67 */
  76. #define RESET_MIPI_HOST 68
  77. #define RESET_AUDIO_LOCKER 69
  78. #define RESET_GE2D 70
  79. /* 71-76 */
  80. #define RESET_AO_CPU_RESET 77
  81. /* 78-95 */
  82. /* RESET3 */
  83. #define RESET_RING_OSCILLATOR 96
  84. /* 97-127 */
  85. /* RESET4 */
  86. /* 128 */
  87. /* 129 */
  88. #define RESET_MIPI_PHY 130
  89. /* 131-140 */
  90. #define RESET_VENCL 141
  91. #define RESET_I2C_MASTER_2 142
  92. #define RESET_I2C_MASTER_1 143
  93. /* 144-159 */
  94. /* RESET5 */
  95. /* 160-191 */
  96. /* RESET6 */
  97. #define RESET_PERIPHS_GENERAL 192
  98. #define RESET_PERIPHS_SPICC 193
  99. /* 194 */
  100. /* 195 */
  101. #define RESET_PERIPHS_I2C_MASTER_0 196
  102. /* 197-200 */
  103. #define RESET_PERIPHS_UART_0 201
  104. #define RESET_PERIPHS_UART_1 202
  105. /* 203-204 */
  106. #define RESET_PERIPHS_SPI_0 205
  107. #define RESET_PERIPHS_I2C_MASTER_3 206
  108. /* 207-223 */
  109. /* RESET7 */
  110. #define RESET_USB_DDR_0 224
  111. #define RESET_USB_DDR_1 225
  112. #define RESET_USB_DDR_2 226
  113. #define RESET_USB_DDR_3 227
  114. /* 228 */
  115. #define RESET_DEVICE_MMC_ARB 229
  116. /* 230 */
  117. #define RESET_VID_LOCK 231
  118. #define RESET_A9_DMC_PIPEL 232
  119. #define RESET_DMC_VPU_PIPEL 233
  120. /* 234-255 */
  121. #endif