altr,rst-mgr-s10.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation. All rights reserved
  4. * Copyright (C) 2016 Altera Corporation. All rights reserved
  5. * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
  6. */
  7. #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
  8. #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
  9. /* MPUMODRST */
  10. #define CPU0_RESET 0
  11. #define CPU1_RESET 1
  12. #define CPU2_RESET 2
  13. #define CPU3_RESET 3
  14. /* PER0MODRST */
  15. #define EMAC0_RESET 32
  16. #define EMAC1_RESET 33
  17. #define EMAC2_RESET 34
  18. #define USB0_RESET 35
  19. #define USB1_RESET 36
  20. #define NAND_RESET 37
  21. /* 38 is empty */
  22. #define SDMMC_RESET 39
  23. #define EMAC0_OCP_RESET 40
  24. #define EMAC1_OCP_RESET 41
  25. #define EMAC2_OCP_RESET 42
  26. #define USB0_OCP_RESET 43
  27. #define USB1_OCP_RESET 44
  28. #define NAND_OCP_RESET 45
  29. /* 46 is empty */
  30. #define SDMMC_OCP_RESET 47
  31. #define DMA_RESET 48
  32. #define SPIM0_RESET 49
  33. #define SPIM1_RESET 50
  34. #define SPIS0_RESET 51
  35. #define SPIS1_RESET 52
  36. #define DMA_OCP_RESET 53
  37. #define EMAC_PTP_RESET 54
  38. /* 55 is empty*/
  39. #define DMAIF0_RESET 56
  40. #define DMAIF1_RESET 57
  41. #define DMAIF2_RESET 58
  42. #define DMAIF3_RESET 59
  43. #define DMAIF4_RESET 60
  44. #define DMAIF5_RESET 61
  45. #define DMAIF6_RESET 62
  46. #define DMAIF7_RESET 63
  47. /* PER1MODRST */
  48. #define WATCHDOG0_RESET 64
  49. #define WATCHDOG1_RESET 65
  50. #define WATCHDOG2_RESET 66
  51. #define WATCHDOG3_RESET 67
  52. #define L4SYSTIMER0_RESET 68
  53. #define L4SYSTIMER1_RESET 69
  54. #define SPTIMER0_RESET 70
  55. #define SPTIMER1_RESET 71
  56. #define I2C0_RESET 72
  57. #define I2C1_RESET 73
  58. #define I2C2_RESET 74
  59. #define I2C3_RESET 75
  60. #define I2C4_RESET 76
  61. /* 77-79 is empty */
  62. #define UART0_RESET 80
  63. #define UART1_RESET 81
  64. /* 82-87 is empty */
  65. #define GPIO0_RESET 88
  66. #define GPIO1_RESET 89
  67. /* BRGMODRST */
  68. #define SOC2FPGA_RESET 96
  69. #define LWHPS2FPGA_RESET 97
  70. #define FPGA2SOC_RESET 98
  71. #define F2SSDRAM0_RESET 99
  72. #define F2SSDRAM1_RESET 100
  73. #define F2SSDRAM2_RESET 101
  74. #define DDRSCH_RESET 102
  75. /* COLDMODRST */
  76. #define CPUPO0_RESET 160
  77. #define CPUPO1_RESET 161
  78. #define CPUPO2_RESET 162
  79. #define CPUPO3_RESET 163
  80. /* 164-167 is empty */
  81. #define L2_RESET 168
  82. /* DBGMODRST */
  83. #define DBG_RESET 224
  84. #define CSDAP_RESET 225
  85. /* TAPMODRST */
  86. #define TAP_RESET 256
  87. #endif