stm32h7-rcc.h 4.1 KB

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  1. /*
  2. * This header provides constants for the STM32H7 RCC IP
  3. */
  4. #ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
  5. #define _DT_BINDINGS_MFD_STM32H7_RCC_H
  6. /* AHB3 */
  7. #define STM32H7_RCC_AHB3_MDMA 0
  8. #define STM32H7_RCC_AHB3_DMA2D 4
  9. #define STM32H7_RCC_AHB3_JPGDEC 5
  10. #define STM32H7_RCC_AHB3_FMC 12
  11. #define STM32H7_RCC_AHB3_QUADSPI 14
  12. #define STM32H7_RCC_AHB3_SDMMC1 16
  13. #define STM32H7_RCC_AHB3_CPU 31
  14. #define STM32H7_RCC_AHB3_CPU1 31
  15. #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
  16. /* AHB1 */
  17. #define STM32H7_RCC_AHB1_DMA1 0
  18. #define STM32H7_RCC_AHB1_DMA2 1
  19. #define STM32H7_RCC_AHB1_ADC12 5
  20. #define STM32H7_RCC_AHB1_ART 14
  21. #define STM32H7_RCC_AHB1_ETH1MAC 15
  22. #define STM32H7_RCC_AHB1_USB1OTG 25
  23. #define STM32H7_RCC_AHB1_USB2OTG 27
  24. #define STM32H7_RCC_AHB1_CPU2 31
  25. #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
  26. /* AHB2 */
  27. #define STM32H7_RCC_AHB2_CAMITF 0
  28. #define STM32H7_RCC_AHB2_CRYPT 4
  29. #define STM32H7_RCC_AHB2_HASH 5
  30. #define STM32H7_RCC_AHB2_RNG 6
  31. #define STM32H7_RCC_AHB2_SDMMC2 9
  32. #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
  33. /* AHB4 */
  34. #define STM32H7_RCC_AHB4_GPIOA 0
  35. #define STM32H7_RCC_AHB4_GPIOB 1
  36. #define STM32H7_RCC_AHB4_GPIOC 2
  37. #define STM32H7_RCC_AHB4_GPIOD 3
  38. #define STM32H7_RCC_AHB4_GPIOE 4
  39. #define STM32H7_RCC_AHB4_GPIOF 5
  40. #define STM32H7_RCC_AHB4_GPIOG 6
  41. #define STM32H7_RCC_AHB4_GPIOH 7
  42. #define STM32H7_RCC_AHB4_GPIOI 8
  43. #define STM32H7_RCC_AHB4_GPIOJ 9
  44. #define STM32H7_RCC_AHB4_GPIOK 10
  45. #define STM32H7_RCC_AHB4_CRC 19
  46. #define STM32H7_RCC_AHB4_BDMA 21
  47. #define STM32H7_RCC_AHB4_ADC3 24
  48. #define STM32H7_RCC_AHB4_HSEM 25
  49. #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
  50. /* APB3 */
  51. #define STM32H7_RCC_APB3_LTDC 3
  52. #define STM32H7_RCC_APB3_DSI 4
  53. #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
  54. /* APB1L */
  55. #define STM32H7_RCC_APB1L_TIM2 0
  56. #define STM32H7_RCC_APB1L_TIM3 1
  57. #define STM32H7_RCC_APB1L_TIM4 2
  58. #define STM32H7_RCC_APB1L_TIM5 3
  59. #define STM32H7_RCC_APB1L_TIM6 4
  60. #define STM32H7_RCC_APB1L_TIM7 5
  61. #define STM32H7_RCC_APB1L_TIM12 6
  62. #define STM32H7_RCC_APB1L_TIM13 7
  63. #define STM32H7_RCC_APB1L_TIM14 8
  64. #define STM32H7_RCC_APB1L_LPTIM1 9
  65. #define STM32H7_RCC_APB1L_SPI2 14
  66. #define STM32H7_RCC_APB1L_SPI3 15
  67. #define STM32H7_RCC_APB1L_SPDIF_RX 16
  68. #define STM32H7_RCC_APB1L_USART2 17
  69. #define STM32H7_RCC_APB1L_USART3 18
  70. #define STM32H7_RCC_APB1L_UART4 19
  71. #define STM32H7_RCC_APB1L_UART5 20
  72. #define STM32H7_RCC_APB1L_I2C1 21
  73. #define STM32H7_RCC_APB1L_I2C2 22
  74. #define STM32H7_RCC_APB1L_I2C3 23
  75. #define STM32H7_RCC_APB1L_HDMICEC 27
  76. #define STM32H7_RCC_APB1L_DAC12 29
  77. #define STM32H7_RCC_APB1L_USART7 30
  78. #define STM32H7_RCC_APB1L_USART8 31
  79. #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
  80. /* APB1H */
  81. #define STM32H7_RCC_APB1H_CRS 1
  82. #define STM32H7_RCC_APB1H_SWP 2
  83. #define STM32H7_RCC_APB1H_OPAMP 4
  84. #define STM32H7_RCC_APB1H_MDIOS 5
  85. #define STM32H7_RCC_APB1H_FDCAN 8
  86. #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
  87. /* APB2 */
  88. #define STM32H7_RCC_APB2_TIM1 0
  89. #define STM32H7_RCC_APB2_TIM8 1
  90. #define STM32H7_RCC_APB2_USART1 4
  91. #define STM32H7_RCC_APB2_USART6 5
  92. #define STM32H7_RCC_APB2_SPI1 12
  93. #define STM32H7_RCC_APB2_SPI4 13
  94. #define STM32H7_RCC_APB2_TIM15 16
  95. #define STM32H7_RCC_APB2_TIM16 17
  96. #define STM32H7_RCC_APB2_TIM17 18
  97. #define STM32H7_RCC_APB2_SPI5 20
  98. #define STM32H7_RCC_APB2_SAI1 22
  99. #define STM32H7_RCC_APB2_SAI2 23
  100. #define STM32H7_RCC_APB2_SAI3 24
  101. #define STM32H7_RCC_APB2_DFSDM1 28
  102. #define STM32H7_RCC_APB2_HRTIM 29
  103. #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
  104. /* APB4 */
  105. #define STM32H7_RCC_APB4_SYSCFG 1
  106. #define STM32H7_RCC_APB4_LPUART1 3
  107. #define STM32H7_RCC_APB4_SPI6 5
  108. #define STM32H7_RCC_APB4_I2C4 7
  109. #define STM32H7_RCC_APB4_LPTIM2 9
  110. #define STM32H7_RCC_APB4_LPTIM3 10
  111. #define STM32H7_RCC_APB4_LPTIM4 11
  112. #define STM32H7_RCC_APB4_LPTIM5 12
  113. #define STM32H7_RCC_APB4_COMP12 14
  114. #define STM32H7_RCC_APB4_VREF 15
  115. #define STM32H7_RCC_APB4_SAI4 21
  116. #define STM32H7_RCC_APB4_TMPSENS 26
  117. #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
  118. #endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */