tegra210-car.h 9.4 KB

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  1. /*
  2. * This header provides constants for binding nvidia,tegra210-car.
  3. *
  4. * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  5. * registers. These IDs often match those in the CAR's RST_DEVICES registers,
  6. * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  7. * this case, those clocks are assigned IDs above 224 in order to highlight
  8. * this issue. Implementations that interpret these clock IDs as bit values
  9. * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  10. * explicitly handle these special cases.
  11. *
  12. * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
  13. * above.
  14. */
  15. #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
  16. #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
  17. /* 0 */
  18. /* 1 */
  19. /* 2 */
  20. #define TEGRA210_CLK_ISPB 3
  21. #define TEGRA210_CLK_RTC 4
  22. #define TEGRA210_CLK_TIMER 5
  23. #define TEGRA210_CLK_UARTA 6
  24. /* 7 (register bit affects uartb and vfir) */
  25. #define TEGRA210_CLK_GPIO 8
  26. #define TEGRA210_CLK_SDMMC2 9
  27. /* 10 (register bit affects spdif_in and spdif_out) */
  28. #define TEGRA210_CLK_I2S1 11
  29. #define TEGRA210_CLK_I2C1 12
  30. /* 13 */
  31. #define TEGRA210_CLK_SDMMC1 14
  32. #define TEGRA210_CLK_SDMMC4 15
  33. /* 16 */
  34. #define TEGRA210_CLK_PWM 17
  35. #define TEGRA210_CLK_I2S2 18
  36. /* 19 */
  37. /* 20 (register bit affects vi and vi_sensor) */
  38. /* 21 */
  39. #define TEGRA210_CLK_USBD 22
  40. #define TEGRA210_CLK_ISP 23
  41. /* 24 */
  42. /* 25 */
  43. #define TEGRA210_CLK_DISP2 26
  44. #define TEGRA210_CLK_DISP1 27
  45. #define TEGRA210_CLK_HOST1X 28
  46. /* 29 */
  47. #define TEGRA210_CLK_I2S0 30
  48. /* 31 */
  49. #define TEGRA210_CLK_MC 32
  50. #define TEGRA210_CLK_AHBDMA 33
  51. #define TEGRA210_CLK_APBDMA 34
  52. /* 35 */
  53. /* 36 */
  54. /* 37 */
  55. #define TEGRA210_CLK_PMC 38
  56. /* 39 (register bit affects fuse and fuse_burn) */
  57. #define TEGRA210_CLK_KFUSE 40
  58. #define TEGRA210_CLK_SBC1 41
  59. /* 42 */
  60. /* 43 */
  61. #define TEGRA210_CLK_SBC2 44
  62. /* 45 */
  63. #define TEGRA210_CLK_SBC3 46
  64. #define TEGRA210_CLK_I2C5 47
  65. #define TEGRA210_CLK_DSIA 48
  66. /* 49 */
  67. /* 50 */
  68. /* 51 */
  69. #define TEGRA210_CLK_CSI 52
  70. /* 53 */
  71. #define TEGRA210_CLK_I2C2 54
  72. #define TEGRA210_CLK_UARTC 55
  73. #define TEGRA210_CLK_MIPI_CAL 56
  74. #define TEGRA210_CLK_EMC 57
  75. #define TEGRA210_CLK_USB2 58
  76. /* 59 */
  77. /* 60 */
  78. /* 61 */
  79. /* 62 */
  80. #define TEGRA210_CLK_BSEV 63
  81. /* 64 */
  82. #define TEGRA210_CLK_UARTD 65
  83. /* 66 */
  84. #define TEGRA210_CLK_I2C3 67
  85. #define TEGRA210_CLK_SBC4 68
  86. #define TEGRA210_CLK_SDMMC3 69
  87. #define TEGRA210_CLK_PCIE 70
  88. #define TEGRA210_CLK_OWR 71
  89. #define TEGRA210_CLK_AFI 72
  90. #define TEGRA210_CLK_CSITE 73
  91. /* 74 */
  92. /* 75 */
  93. /* 76 */
  94. /* 77 */
  95. #define TEGRA210_CLK_SOC_THERM 78
  96. #define TEGRA210_CLK_DTV 79
  97. /* 80 */
  98. #define TEGRA210_CLK_I2CSLOW 81
  99. #define TEGRA210_CLK_DSIB 82
  100. #define TEGRA210_CLK_TSEC 83
  101. /* 84 */
  102. /* 85 */
  103. /* 86 */
  104. /* 87 */
  105. /* 88 */
  106. #define TEGRA210_CLK_XUSB_HOST 89
  107. /* 90 */
  108. /* 91 */
  109. #define TEGRA210_CLK_CSUS 92
  110. /* 93 */
  111. /* 94 */
  112. /* 95 (bit affects xusb_dev and xusb_dev_src) */
  113. /* 96 */
  114. /* 97 */
  115. /* 98 */
  116. #define TEGRA210_CLK_MSELECT 99
  117. #define TEGRA210_CLK_TSENSOR 100
  118. #define TEGRA210_CLK_I2S3 101
  119. #define TEGRA210_CLK_I2S4 102
  120. #define TEGRA210_CLK_I2C4 103
  121. /* 104 */
  122. /* 105 */
  123. #define TEGRA210_CLK_D_AUDIO 106
  124. #define TEGRA210_CLK_APB2APE 107
  125. /* 108 */
  126. /* 109 */
  127. /* 110 */
  128. #define TEGRA210_CLK_HDA2CODEC_2X 111
  129. /* 112 */
  130. /* 113 */
  131. /* 114 */
  132. /* 115 */
  133. /* 116 */
  134. /* 117 */
  135. #define TEGRA210_CLK_SPDIF_2X 118
  136. #define TEGRA210_CLK_ACTMON 119
  137. #define TEGRA210_CLK_EXTERN1 120
  138. #define TEGRA210_CLK_EXTERN2 121
  139. #define TEGRA210_CLK_EXTERN3 122
  140. #define TEGRA210_CLK_SATA_OOB 123
  141. #define TEGRA210_CLK_SATA 124
  142. #define TEGRA210_CLK_HDA 125
  143. /* 126 */
  144. /* 127 */
  145. #define TEGRA210_CLK_HDA2HDMI 128
  146. /* 129 */
  147. /* 130 */
  148. /* 131 */
  149. /* 132 */
  150. /* 133 */
  151. /* 134 */
  152. /* 135 */
  153. /* 136 */
  154. /* 137 */
  155. /* 138 */
  156. /* 139 */
  157. /* 140 */
  158. /* 141 */
  159. /* 142 */
  160. /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
  161. #define TEGRA210_CLK_XUSB_GATE 143
  162. #define TEGRA210_CLK_CILAB 144
  163. #define TEGRA210_CLK_CILCD 145
  164. #define TEGRA210_CLK_CILE 146
  165. #define TEGRA210_CLK_DSIALP 147
  166. #define TEGRA210_CLK_DSIBLP 148
  167. #define TEGRA210_CLK_ENTROPY 149
  168. /* 150 */
  169. /* 151 */
  170. /* 152 */
  171. /* 153 */
  172. /* 154 */
  173. /* 155 (bit affects dfll_ref and dfll_soc) */
  174. #define TEGRA210_CLK_XUSB_SS 156
  175. /* 157 */
  176. /* 158 */
  177. /* 159 */
  178. /* 160 */
  179. #define TEGRA210_CLK_DMIC1 161
  180. #define TEGRA210_CLK_DMIC2 162
  181. /* 163 */
  182. /* 164 */
  183. /* 165 */
  184. #define TEGRA210_CLK_I2C6 166
  185. /* 167 */
  186. /* 168 */
  187. /* 169 */
  188. /* 170 */
  189. #define TEGRA210_CLK_VIM2_CLK 171
  190. /* 172 */
  191. #define TEGRA210_CLK_MIPIBIF 173
  192. /* 174 */
  193. /* 175 */
  194. /* 176 */
  195. #define TEGRA210_CLK_CLK72MHZ 177
  196. #define TEGRA210_CLK_VIC03 178
  197. /* 179 */
  198. /* 180 */
  199. #define TEGRA210_CLK_DPAUX 181
  200. #define TEGRA210_CLK_SOR0 182
  201. #define TEGRA210_CLK_SOR1 183
  202. #define TEGRA210_CLK_GPU 184
  203. #define TEGRA210_CLK_DBGAPB 185
  204. /* 186 */
  205. #define TEGRA210_CLK_PLL_P_OUT_ADSP 187
  206. /* 188 */
  207. #define TEGRA210_CLK_PLL_G_REF 189
  208. /* 190 */
  209. /* 191 */
  210. /* 192 */
  211. #define TEGRA210_CLK_SDMMC_LEGACY 193
  212. #define TEGRA210_CLK_NVDEC 194
  213. #define TEGRA210_CLK_NVJPG 195
  214. /* 196 */
  215. #define TEGRA210_CLK_DMIC3 197
  216. #define TEGRA210_CLK_APE 198
  217. /* 199 */
  218. /* 200 */
  219. /* 201 */
  220. #define TEGRA210_CLK_MAUD 202
  221. /* 203 */
  222. /* 204 */
  223. /* 205 */
  224. #define TEGRA210_CLK_TSECB 206
  225. #define TEGRA210_CLK_DPAUX1 207
  226. #define TEGRA210_CLK_VI_I2C 208
  227. #define TEGRA210_CLK_HSIC_TRK 209
  228. #define TEGRA210_CLK_USB2_TRK 210
  229. #define TEGRA210_CLK_QSPI 211
  230. #define TEGRA210_CLK_UARTAPE 212
  231. /* 213 */
  232. /* 214 */
  233. /* 215 */
  234. /* 216 */
  235. /* 217 */
  236. /* 218 */
  237. #define TEGRA210_CLK_NVENC 219
  238. /* 220 */
  239. /* 221 */
  240. #define TEGRA210_CLK_SOR_SAFE 222
  241. #define TEGRA210_CLK_PLL_P_OUT_CPU 223
  242. #define TEGRA210_CLK_UARTB 224
  243. #define TEGRA210_CLK_VFIR 225
  244. #define TEGRA210_CLK_SPDIF_IN 226
  245. #define TEGRA210_CLK_SPDIF_OUT 227
  246. #define TEGRA210_CLK_VI 228
  247. #define TEGRA210_CLK_VI_SENSOR 229
  248. #define TEGRA210_CLK_FUSE 230
  249. #define TEGRA210_CLK_FUSE_BURN 231
  250. #define TEGRA210_CLK_CLK_32K 232
  251. #define TEGRA210_CLK_CLK_M 233
  252. #define TEGRA210_CLK_CLK_M_DIV2 234
  253. #define TEGRA210_CLK_CLK_M_DIV4 235
  254. #define TEGRA210_CLK_PLL_REF 236
  255. #define TEGRA210_CLK_PLL_C 237
  256. #define TEGRA210_CLK_PLL_C_OUT1 238
  257. #define TEGRA210_CLK_PLL_C2 239
  258. #define TEGRA210_CLK_PLL_C3 240
  259. #define TEGRA210_CLK_PLL_M 241
  260. #define TEGRA210_CLK_PLL_M_OUT1 242
  261. #define TEGRA210_CLK_PLL_P 243
  262. #define TEGRA210_CLK_PLL_P_OUT1 244
  263. #define TEGRA210_CLK_PLL_P_OUT2 245
  264. #define TEGRA210_CLK_PLL_P_OUT3 246
  265. #define TEGRA210_CLK_PLL_P_OUT4 247
  266. #define TEGRA210_CLK_PLL_A 248
  267. #define TEGRA210_CLK_PLL_A_OUT0 249
  268. #define TEGRA210_CLK_PLL_D 250
  269. #define TEGRA210_CLK_PLL_D_OUT0 251
  270. #define TEGRA210_CLK_PLL_D2 252
  271. #define TEGRA210_CLK_PLL_D2_OUT0 253
  272. #define TEGRA210_CLK_PLL_U 254
  273. #define TEGRA210_CLK_PLL_U_480M 255
  274. #define TEGRA210_CLK_PLL_U_60M 256
  275. #define TEGRA210_CLK_PLL_U_48M 257
  276. /* 258 */
  277. #define TEGRA210_CLK_PLL_X 259
  278. #define TEGRA210_CLK_PLL_X_OUT0 260
  279. #define TEGRA210_CLK_PLL_RE_VCO 261
  280. #define TEGRA210_CLK_PLL_RE_OUT 262
  281. #define TEGRA210_CLK_PLL_E 263
  282. #define TEGRA210_CLK_SPDIF_IN_SYNC 264
  283. #define TEGRA210_CLK_I2S0_SYNC 265
  284. #define TEGRA210_CLK_I2S1_SYNC 266
  285. #define TEGRA210_CLK_I2S2_SYNC 267
  286. #define TEGRA210_CLK_I2S3_SYNC 268
  287. #define TEGRA210_CLK_I2S4_SYNC 269
  288. #define TEGRA210_CLK_VIMCLK_SYNC 270
  289. #define TEGRA210_CLK_AUDIO0 271
  290. #define TEGRA210_CLK_AUDIO1 272
  291. #define TEGRA210_CLK_AUDIO2 273
  292. #define TEGRA210_CLK_AUDIO3 274
  293. #define TEGRA210_CLK_AUDIO4 275
  294. #define TEGRA210_CLK_SPDIF 276
  295. #define TEGRA210_CLK_CLK_OUT_1 277
  296. #define TEGRA210_CLK_CLK_OUT_2 278
  297. #define TEGRA210_CLK_CLK_OUT_3 279
  298. #define TEGRA210_CLK_BLINK 280
  299. /* 281 */
  300. /* 282 */
  301. /* 283 */
  302. #define TEGRA210_CLK_XUSB_HOST_SRC 284
  303. #define TEGRA210_CLK_XUSB_FALCON_SRC 285
  304. #define TEGRA210_CLK_XUSB_FS_SRC 286
  305. #define TEGRA210_CLK_XUSB_SS_SRC 287
  306. #define TEGRA210_CLK_XUSB_DEV_SRC 288
  307. #define TEGRA210_CLK_XUSB_DEV 289
  308. #define TEGRA210_CLK_XUSB_HS_SRC 290
  309. #define TEGRA210_CLK_SCLK 291
  310. #define TEGRA210_CLK_HCLK 292
  311. #define TEGRA210_CLK_PCLK 293
  312. #define TEGRA210_CLK_CCLK_G 294
  313. #define TEGRA210_CLK_CCLK_LP 295
  314. #define TEGRA210_CLK_DFLL_REF 296
  315. #define TEGRA210_CLK_DFLL_SOC 297
  316. #define TEGRA210_CLK_VI_SENSOR2 298
  317. #define TEGRA210_CLK_PLL_P_OUT5 299
  318. #define TEGRA210_CLK_CML0 300
  319. #define TEGRA210_CLK_CML1 301
  320. #define TEGRA210_CLK_PLL_C4 302
  321. #define TEGRA210_CLK_PLL_DP 303
  322. #define TEGRA210_CLK_PLL_E_MUX 304
  323. #define TEGRA210_CLK_PLL_MB 305
  324. #define TEGRA210_CLK_PLL_A1 306
  325. #define TEGRA210_CLK_PLL_D_DSI_OUT 307
  326. #define TEGRA210_CLK_PLL_C4_OUT0 308
  327. #define TEGRA210_CLK_PLL_C4_OUT1 309
  328. #define TEGRA210_CLK_PLL_C4_OUT2 310
  329. #define TEGRA210_CLK_PLL_C4_OUT3 311
  330. #define TEGRA210_CLK_PLL_U_OUT 312
  331. #define TEGRA210_CLK_PLL_U_OUT1 313
  332. #define TEGRA210_CLK_PLL_U_OUT2 314
  333. #define TEGRA210_CLK_USB2_HSIC_TRK 315
  334. #define TEGRA210_CLK_PLL_P_OUT_HSIO 316
  335. #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
  336. #define TEGRA210_CLK_XUSB_SSP_SRC 318
  337. #define TEGRA210_CLK_PLL_RE_OUT1 319
  338. /* 320 */
  339. /* 321 */
  340. /* 322 */
  341. /* 323 */
  342. /* 324 */
  343. /* 325 */
  344. /* 326 */
  345. /* 327 */
  346. /* 328 */
  347. /* 329 */
  348. /* 330 */
  349. /* 331 */
  350. /* 332 */
  351. /* 333 */
  352. /* 334 */
  353. /* 335 */
  354. /* 336 */
  355. /* 337 */
  356. /* 338 */
  357. /* 339 */
  358. /* 340 */
  359. /* 341 */
  360. /* 342 */
  361. /* 343 */
  362. /* 344 */
  363. /* 345 */
  364. /* 346 */
  365. /* 347 */
  366. /* 348 */
  367. /* 349 */
  368. #define TEGRA210_CLK_AUDIO0_MUX 350
  369. #define TEGRA210_CLK_AUDIO1_MUX 351
  370. #define TEGRA210_CLK_AUDIO2_MUX 352
  371. #define TEGRA210_CLK_AUDIO3_MUX 353
  372. #define TEGRA210_CLK_AUDIO4_MUX 354
  373. #define TEGRA210_CLK_SPDIF_MUX 355
  374. #define TEGRA210_CLK_CLK_OUT_1_MUX 356
  375. #define TEGRA210_CLK_CLK_OUT_2_MUX 357
  376. #define TEGRA210_CLK_CLK_OUT_3_MUX 358
  377. #define TEGRA210_CLK_DSIA_MUX 359
  378. #define TEGRA210_CLK_DSIB_MUX 360
  379. #define TEGRA210_CLK_SOR0_LVDS 361
  380. #define TEGRA210_CLK_XUSB_SS_DIV2 362
  381. #define TEGRA210_CLK_PLL_M_UD 363
  382. #define TEGRA210_CLK_PLL_C_UD 364
  383. #define TEGRA210_CLK_SCLK_MUX 365
  384. #define TEGRA210_CLK_CLK_MAX 366
  385. #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */