stm32mp1-clks.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
  2. /*
  3. * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  4. * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
  5. */
  6. #ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
  7. #define _DT_BINDINGS_STM32MP1_CLKS_H_
  8. /* OSCILLATOR clocks */
  9. #define CK_HSE 0
  10. #define CK_CSI 1
  11. #define CK_LSI 2
  12. #define CK_LSE 3
  13. #define CK_HSI 4
  14. #define CK_HSE_DIV2 5
  15. /* Bus clocks */
  16. #define TIM2 6
  17. #define TIM3 7
  18. #define TIM4 8
  19. #define TIM5 9
  20. #define TIM6 10
  21. #define TIM7 11
  22. #define TIM12 12
  23. #define TIM13 13
  24. #define TIM14 14
  25. #define LPTIM1 15
  26. #define SPI2 16
  27. #define SPI3 17
  28. #define USART2 18
  29. #define USART3 19
  30. #define UART4 20
  31. #define UART5 21
  32. #define UART7 22
  33. #define UART8 23
  34. #define I2C1 24
  35. #define I2C2 25
  36. #define I2C3 26
  37. #define I2C5 27
  38. #define SPDIF 28
  39. #define CEC 29
  40. #define DAC12 30
  41. #define MDIO 31
  42. #define TIM1 32
  43. #define TIM8 33
  44. #define TIM15 34
  45. #define TIM16 35
  46. #define TIM17 36
  47. #define SPI1 37
  48. #define SPI4 38
  49. #define SPI5 39
  50. #define USART6 40
  51. #define SAI1 41
  52. #define SAI2 42
  53. #define SAI3 43
  54. #define DFSDM 44
  55. #define FDCAN 45
  56. #define LPTIM2 46
  57. #define LPTIM3 47
  58. #define LPTIM4 48
  59. #define LPTIM5 49
  60. #define SAI4 50
  61. #define SYSCFG 51
  62. #define VREF 52
  63. #define TMPSENS 53
  64. #define PMBCTRL 54
  65. #define HDP 55
  66. #define LTDC 56
  67. #define DSI 57
  68. #define IWDG2 58
  69. #define USBPHY 59
  70. #define STGENRO 60
  71. #define SPI6 61
  72. #define I2C4 62
  73. #define I2C6 63
  74. #define USART1 64
  75. #define RTCAPB 65
  76. #define TZC1 66
  77. #define TZPC 67
  78. #define IWDG1 68
  79. #define BSEC 69
  80. #define STGEN 70
  81. #define DMA1 71
  82. #define DMA2 72
  83. #define DMAMUX 73
  84. #define ADC12 74
  85. #define USBO 75
  86. #define SDMMC3 76
  87. #define DCMI 77
  88. #define CRYP2 78
  89. #define HASH2 79
  90. #define RNG2 80
  91. #define CRC2 81
  92. #define HSEM 82
  93. #define IPCC 83
  94. #define GPIOA 84
  95. #define GPIOB 85
  96. #define GPIOC 86
  97. #define GPIOD 87
  98. #define GPIOE 88
  99. #define GPIOF 89
  100. #define GPIOG 90
  101. #define GPIOH 91
  102. #define GPIOI 92
  103. #define GPIOJ 93
  104. #define GPIOK 94
  105. #define GPIOZ 95
  106. #define CRYP1 96
  107. #define HASH1 97
  108. #define RNG1 98
  109. #define BKPSRAM 99
  110. #define MDMA 100
  111. #define GPU 101
  112. #define ETHCK 102
  113. #define ETHTX 103
  114. #define ETHRX 104
  115. #define ETHMAC 105
  116. #define FMC 106
  117. #define QSPI 107
  118. #define SDMMC1 108
  119. #define SDMMC2 109
  120. #define CRC1 110
  121. #define USBH 111
  122. #define ETHSTP 112
  123. #define TZC2 113
  124. /* Kernel clocks */
  125. #define SDMMC1_K 118
  126. #define SDMMC2_K 119
  127. #define SDMMC3_K 120
  128. #define FMC_K 121
  129. #define QSPI_K 122
  130. #define ETHCK_K 123
  131. #define RNG1_K 124
  132. #define RNG2_K 125
  133. #define GPU_K 126
  134. #define USBPHY_K 127
  135. #define STGEN_K 128
  136. #define SPDIF_K 129
  137. #define SPI1_K 130
  138. #define SPI2_K 131
  139. #define SPI3_K 132
  140. #define SPI4_K 133
  141. #define SPI5_K 134
  142. #define SPI6_K 135
  143. #define CEC_K 136
  144. #define I2C1_K 137
  145. #define I2C2_K 138
  146. #define I2C3_K 139
  147. #define I2C4_K 140
  148. #define I2C5_K 141
  149. #define I2C6_K 142
  150. #define LPTIM1_K 143
  151. #define LPTIM2_K 144
  152. #define LPTIM3_K 145
  153. #define LPTIM4_K 146
  154. #define LPTIM5_K 147
  155. #define USART1_K 148
  156. #define USART2_K 149
  157. #define USART3_K 150
  158. #define UART4_K 151
  159. #define UART5_K 152
  160. #define USART6_K 153
  161. #define UART7_K 154
  162. #define UART8_K 155
  163. #define DFSDM_K 156
  164. #define FDCAN_K 157
  165. #define SAI1_K 158
  166. #define SAI2_K 159
  167. #define SAI3_K 160
  168. #define SAI4_K 161
  169. #define ADC12_K 162
  170. #define DSI_K 163
  171. #define DSI_PX 164
  172. #define ADFSDM_K 165
  173. #define USBO_K 166
  174. #define LTDC_PX 167
  175. #define DAC12_K 168
  176. #define ETHPTP_K 169
  177. /* PLL */
  178. #define PLL1 176
  179. #define PLL2 177
  180. #define PLL3 178
  181. #define PLL4 179
  182. /* ODF */
  183. #define PLL1_P 180
  184. #define PLL1_Q 181
  185. #define PLL1_R 182
  186. #define PLL2_P 183
  187. #define PLL2_Q 184
  188. #define PLL2_R 185
  189. #define PLL3_P 186
  190. #define PLL3_Q 187
  191. #define PLL3_R 188
  192. #define PLL4_P 189
  193. #define PLL4_Q 190
  194. #define PLL4_R 191
  195. /* AUX */
  196. #define RTC 192
  197. /* MCLK */
  198. #define CK_PER 193
  199. #define CK_MPU 194
  200. #define CK_AXI 195
  201. #define CK_MCU 196
  202. /* Time base */
  203. #define TIM2_K 197
  204. #define TIM3_K 198
  205. #define TIM4_K 199
  206. #define TIM5_K 200
  207. #define TIM6_K 201
  208. #define TIM7_K 202
  209. #define TIM12_K 203
  210. #define TIM13_K 204
  211. #define TIM14_K 205
  212. #define TIM1_K 206
  213. #define TIM8_K 207
  214. #define TIM15_K 208
  215. #define TIM16_K 209
  216. #define TIM17_K 210
  217. /* MCO clocks */
  218. #define CK_MCO1 211
  219. #define CK_MCO2 212
  220. /* TRACE & DEBUG clocks */
  221. #define CK_DBG 214
  222. #define CK_TRACE 215
  223. /* DDR */
  224. #define DDRC1 220
  225. #define DDRC1LP 221
  226. #define DDRC2 222
  227. #define DDRC2LP 223
  228. #define DDRPHYC 224
  229. #define DDRPHYCLP 225
  230. #define DDRCAPB 226
  231. #define DDRCAPBLP 227
  232. #define AXIDCG 228
  233. #define DDRPHYCAPB 229
  234. #define DDRPHYCAPBLP 230
  235. #define DDRPERFM 231
  236. #define STM32MP1_LAST_CLK 232
  237. #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */