rk3328-cru.h 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
  6. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
  7. /* core clocks */
  8. #define PLL_APLL 1
  9. #define PLL_DPLL 2
  10. #define PLL_CPLL 3
  11. #define PLL_GPLL 4
  12. #define PLL_NPLL 5
  13. #define ARMCLK 6
  14. /* sclk gates (special clocks) */
  15. #define SCLK_RTC32K 30
  16. #define SCLK_SDMMC_EXT 31
  17. #define SCLK_SPI 32
  18. #define SCLK_SDMMC 33
  19. #define SCLK_SDIO 34
  20. #define SCLK_EMMC 35
  21. #define SCLK_TSADC 36
  22. #define SCLK_SARADC 37
  23. #define SCLK_UART0 38
  24. #define SCLK_UART1 39
  25. #define SCLK_UART2 40
  26. #define SCLK_I2S0 41
  27. #define SCLK_I2S1 42
  28. #define SCLK_I2S2 43
  29. #define SCLK_I2S1_OUT 44
  30. #define SCLK_I2S2_OUT 45
  31. #define SCLK_SPDIF 46
  32. #define SCLK_TIMER0 47
  33. #define SCLK_TIMER1 48
  34. #define SCLK_TIMER2 49
  35. #define SCLK_TIMER3 50
  36. #define SCLK_TIMER4 51
  37. #define SCLK_TIMER5 52
  38. #define SCLK_WIFI 53
  39. #define SCLK_CIF_OUT 54
  40. #define SCLK_I2C0 55
  41. #define SCLK_I2C1 56
  42. #define SCLK_I2C2 57
  43. #define SCLK_I2C3 58
  44. #define SCLK_CRYPTO 59
  45. #define SCLK_PWM 60
  46. #define SCLK_PDM 61
  47. #define SCLK_EFUSE 62
  48. #define SCLK_OTP 63
  49. #define SCLK_DDRCLK 64
  50. #define SCLK_VDEC_CABAC 65
  51. #define SCLK_VDEC_CORE 66
  52. #define SCLK_VENC_DSP 67
  53. #define SCLK_VENC_CORE 68
  54. #define SCLK_RGA 69
  55. #define SCLK_HDMI_SFC 70
  56. #define SCLK_HDMI_CEC 71
  57. #define SCLK_USB3_REF 72
  58. #define SCLK_USB3_SUSPEND 73
  59. #define SCLK_SDMMC_DRV 74
  60. #define SCLK_SDIO_DRV 75
  61. #define SCLK_EMMC_DRV 76
  62. #define SCLK_SDMMC_EXT_DRV 77
  63. #define SCLK_SDMMC_SAMPLE 78
  64. #define SCLK_SDIO_SAMPLE 79
  65. #define SCLK_EMMC_SAMPLE 80
  66. #define SCLK_SDMMC_EXT_SAMPLE 81
  67. #define SCLK_VOP 82
  68. #define SCLK_MAC2PHY_RXTX 83
  69. #define SCLK_MAC2PHY_SRC 84
  70. #define SCLK_MAC2PHY_REF 85
  71. #define SCLK_MAC2PHY_OUT 86
  72. #define SCLK_MAC2IO_RX 87
  73. #define SCLK_MAC2IO_TX 88
  74. #define SCLK_MAC2IO_REFOUT 89
  75. #define SCLK_MAC2IO_REF 90
  76. #define SCLK_MAC2IO_OUT 91
  77. #define SCLK_TSP 92
  78. #define SCLK_HSADC_TSP 93
  79. #define SCLK_USB3PHY_REF 94
  80. #define SCLK_REF_USB3OTG 95
  81. #define SCLK_USB3OTG_REF 96
  82. #define SCLK_USB3OTG_SUSPEND 97
  83. #define SCLK_REF_USB3OTG_SRC 98
  84. #define SCLK_MAC2IO_SRC 99
  85. #define SCLK_MAC2IO 100
  86. #define SCLK_MAC2PHY 101
  87. #define SCLK_MAC2IO_EXT 102
  88. /* dclk gates */
  89. #define DCLK_LCDC 180
  90. #define DCLK_HDMIPHY 181
  91. #define HDMIPHY 182
  92. #define USB480M 183
  93. #define DCLK_LCDC_SRC 184
  94. /* aclk gates */
  95. #define ACLK_AXISRAM 190
  96. #define ACLK_VOP_PRE 191
  97. #define ACLK_USB3OTG 192
  98. #define ACLK_RGA_PRE 193
  99. #define ACLK_DMAC 194
  100. #define ACLK_GPU 195
  101. #define ACLK_BUS_PRE 196
  102. #define ACLK_PERI_PRE 197
  103. #define ACLK_RKVDEC_PRE 198
  104. #define ACLK_RKVDEC 199
  105. #define ACLK_RKVENC 200
  106. #define ACLK_VPU_PRE 201
  107. #define ACLK_VIO_PRE 202
  108. #define ACLK_VPU 203
  109. #define ACLK_VIO 204
  110. #define ACLK_VOP 205
  111. #define ACLK_GMAC 206
  112. #define ACLK_H265 207
  113. #define ACLK_H264 208
  114. #define ACLK_MAC2PHY 209
  115. #define ACLK_MAC2IO 210
  116. #define ACLK_DCF 211
  117. #define ACLK_TSP 212
  118. #define ACLK_PERI 213
  119. #define ACLK_RGA 214
  120. #define ACLK_IEP 215
  121. #define ACLK_CIF 216
  122. #define ACLK_HDCP 217
  123. /* pclk gates */
  124. #define PCLK_GPIO0 300
  125. #define PCLK_GPIO1 301
  126. #define PCLK_GPIO2 302
  127. #define PCLK_GPIO3 303
  128. #define PCLK_GRF 304
  129. #define PCLK_I2C0 305
  130. #define PCLK_I2C1 306
  131. #define PCLK_I2C2 307
  132. #define PCLK_I2C3 308
  133. #define PCLK_SPI 309
  134. #define PCLK_UART0 310
  135. #define PCLK_UART1 311
  136. #define PCLK_UART2 312
  137. #define PCLK_TSADC 313
  138. #define PCLK_PWM 314
  139. #define PCLK_TIMER 315
  140. #define PCLK_BUS_PRE 316
  141. #define PCLK_PERI_PRE 317
  142. #define PCLK_HDMI_CTRL 318
  143. #define PCLK_HDMI_PHY 319
  144. #define PCLK_GMAC 320
  145. #define PCLK_H265 321
  146. #define PCLK_MAC2PHY 322
  147. #define PCLK_MAC2IO 323
  148. #define PCLK_USB3PHY_OTG 324
  149. #define PCLK_USB3PHY_PIPE 325
  150. #define PCLK_USB3_GRF 326
  151. #define PCLK_USB2_GRF 327
  152. #define PCLK_HDMIPHY 328
  153. #define PCLK_DDR 329
  154. #define PCLK_PERI 330
  155. #define PCLK_HDMI 331
  156. #define PCLK_HDCP 332
  157. #define PCLK_DCF 333
  158. #define PCLK_SARADC 334
  159. /* hclk gates */
  160. #define HCLK_PERI 408
  161. #define HCLK_TSP 409
  162. #define HCLK_GMAC 410
  163. #define HCLK_I2S0_8CH 411
  164. #define HCLK_I2S1_8CH 413
  165. #define HCLK_I2S2_2CH 413
  166. #define HCLK_SPDIF_8CH 414
  167. #define HCLK_VOP 415
  168. #define HCLK_NANDC 416
  169. #define HCLK_SDMMC 417
  170. #define HCLK_SDIO 418
  171. #define HCLK_EMMC 419
  172. #define HCLK_SDMMC_EXT 420
  173. #define HCLK_RKVDEC_PRE 421
  174. #define HCLK_RKVDEC 422
  175. #define HCLK_RKVENC 423
  176. #define HCLK_VPU_PRE 424
  177. #define HCLK_VIO_PRE 425
  178. #define HCLK_VPU 426
  179. #define HCLK_VIO 427
  180. #define HCLK_BUS_PRE 428
  181. #define HCLK_PERI_PRE 429
  182. #define HCLK_H264 430
  183. #define HCLK_CIF 431
  184. #define HCLK_OTG_PMU 432
  185. #define HCLK_OTG 433
  186. #define HCLK_HOST0 434
  187. #define HCLK_HOST0_ARB 435
  188. #define HCLK_CRYPTO_MST 436
  189. #define HCLK_CRYPTO_SLV 437
  190. #define HCLK_PDM 438
  191. #define HCLK_IEP 439
  192. #define HCLK_RGA 440
  193. #define HCLK_HDCP 441
  194. #define CLK_NR_CLKS (HCLK_HDCP + 1)
  195. #define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
  196. /* soft-reset indices */
  197. #define SRST_CORE0_PO 0
  198. #define SRST_CORE1_PO 1
  199. #define SRST_CORE2_PO 2
  200. #define SRST_CORE3_PO 3
  201. #define SRST_CORE0 4
  202. #define SRST_CORE1 5
  203. #define SRST_CORE2 6
  204. #define SRST_CORE3 7
  205. #define SRST_CORE0_DBG 8
  206. #define SRST_CORE1_DBG 9
  207. #define SRST_CORE2_DBG 10
  208. #define SRST_CORE3_DBG 11
  209. #define SRST_TOPDBG 12
  210. #define SRST_CORE_NIU 13
  211. #define SRST_STRC_A 14
  212. #define SRST_L2C 15
  213. #define SRST_A53_GIC 18
  214. #define SRST_DAP 19
  215. #define SRST_PMU_P 21
  216. #define SRST_EFUSE 22
  217. #define SRST_BUSSYS_H 23
  218. #define SRST_BUSSYS_P 24
  219. #define SRST_SPDIF 25
  220. #define SRST_INTMEM 26
  221. #define SRST_ROM 27
  222. #define SRST_GPIO0 28
  223. #define SRST_GPIO1 29
  224. #define SRST_GPIO2 30
  225. #define SRST_GPIO3 31
  226. #define SRST_I2S0 32
  227. #define SRST_I2S1 33
  228. #define SRST_I2S2 34
  229. #define SRST_I2S0_H 35
  230. #define SRST_I2S1_H 36
  231. #define SRST_I2S2_H 37
  232. #define SRST_UART0 38
  233. #define SRST_UART1 39
  234. #define SRST_UART2 40
  235. #define SRST_UART0_P 41
  236. #define SRST_UART1_P 42
  237. #define SRST_UART2_P 43
  238. #define SRST_I2C0 44
  239. #define SRST_I2C1 45
  240. #define SRST_I2C2 46
  241. #define SRST_I2C3 47
  242. #define SRST_I2C0_P 48
  243. #define SRST_I2C1_P 49
  244. #define SRST_I2C2_P 50
  245. #define SRST_I2C3_P 51
  246. #define SRST_EFUSE_SE_P 52
  247. #define SRST_EFUSE_NS_P 53
  248. #define SRST_PWM0 54
  249. #define SRST_PWM0_P 55
  250. #define SRST_DMA 56
  251. #define SRST_TSP_A 57
  252. #define SRST_TSP_H 58
  253. #define SRST_TSP 59
  254. #define SRST_TSP_HSADC 60
  255. #define SRST_DCF_A 61
  256. #define SRST_DCF_P 62
  257. #define SRST_SCR 64
  258. #define SRST_SPI 65
  259. #define SRST_TSADC 66
  260. #define SRST_TSADC_P 67
  261. #define SRST_CRYPTO 68
  262. #define SRST_SGRF 69
  263. #define SRST_GRF 70
  264. #define SRST_USB_GRF 71
  265. #define SRST_TIMER_6CH_P 72
  266. #define SRST_TIMER0 73
  267. #define SRST_TIMER1 74
  268. #define SRST_TIMER2 75
  269. #define SRST_TIMER3 76
  270. #define SRST_TIMER4 77
  271. #define SRST_TIMER5 78
  272. #define SRST_USB3GRF 79
  273. #define SRST_PHYNIU 80
  274. #define SRST_HDMIPHY 81
  275. #define SRST_VDAC 82
  276. #define SRST_ACODEC_p 83
  277. #define SRST_SARADC 85
  278. #define SRST_SARADC_P 86
  279. #define SRST_GRF_DDR 87
  280. #define SRST_DFIMON 88
  281. #define SRST_MSCH 89
  282. #define SRST_DDRMSCH 91
  283. #define SRST_DDRCTRL 92
  284. #define SRST_DDRCTRL_P 93
  285. #define SRST_DDRPHY 94
  286. #define SRST_DDRPHY_P 95
  287. #define SRST_GMAC_NIU_A 96
  288. #define SRST_GMAC_NIU_P 97
  289. #define SRST_GMAC2PHY_A 98
  290. #define SRST_GMAC2IO_A 99
  291. #define SRST_MACPHY 100
  292. #define SRST_OTP_PHY 101
  293. #define SRST_GPU_A 102
  294. #define SRST_GPU_NIU_A 103
  295. #define SRST_SDMMCEXT 104
  296. #define SRST_PERIPH_NIU_A 105
  297. #define SRST_PERIHP_NIU_H 106
  298. #define SRST_PERIHP_P 107
  299. #define SRST_PERIPHSYS_H 108
  300. #define SRST_MMC0 109
  301. #define SRST_SDIO 110
  302. #define SRST_EMMC 111
  303. #define SRST_USB2OTG_H 112
  304. #define SRST_USB2OTG 113
  305. #define SRST_USB2OTG_ADP 114
  306. #define SRST_USB2HOST_H 115
  307. #define SRST_USB2HOST_ARB 116
  308. #define SRST_USB2HOST_AUX 117
  309. #define SRST_USB2HOST_EHCIPHY 118
  310. #define SRST_USB2HOST_UTMI 119
  311. #define SRST_USB3OTG 120
  312. #define SRST_USBPOR 121
  313. #define SRST_USB2OTG_UTMI 122
  314. #define SRST_USB2HOST_PHY_UTMI 123
  315. #define SRST_USB3OTG_UTMI 124
  316. #define SRST_USB3PHY_U2 125
  317. #define SRST_USB3PHY_U3 126
  318. #define SRST_USB3PHY_PIPE 127
  319. #define SRST_VIO_A 128
  320. #define SRST_VIO_BUS_H 129
  321. #define SRST_VIO_H2P_H 130
  322. #define SRST_VIO_ARBI_H 131
  323. #define SRST_VOP_NIU_A 132
  324. #define SRST_VOP_A 133
  325. #define SRST_VOP_H 134
  326. #define SRST_VOP_D 135
  327. #define SRST_RGA 136
  328. #define SRST_RGA_NIU_A 137
  329. #define SRST_RGA_A 138
  330. #define SRST_RGA_H 139
  331. #define SRST_IEP_A 140
  332. #define SRST_IEP_H 141
  333. #define SRST_HDMI 142
  334. #define SRST_HDMI_P 143
  335. #define SRST_HDCP_A 144
  336. #define SRST_HDCP 145
  337. #define SRST_HDCP_H 146
  338. #define SRST_CIF_A 147
  339. #define SRST_CIF_H 148
  340. #define SRST_CIF_P 149
  341. #define SRST_OTP_P 150
  342. #define SRST_OTP_SBPI 151
  343. #define SRST_OTP_USER 152
  344. #define SRST_DDRCTRL_A 153
  345. #define SRST_DDRSTDY_P 154
  346. #define SRST_DDRSTDY 155
  347. #define SRST_PDM_H 156
  348. #define SRST_PDM 157
  349. #define SRST_USB3PHY_OTG_P 158
  350. #define SRST_USB3PHY_PIPE_P 159
  351. #define SRST_VCODEC_A 160
  352. #define SRST_VCODEC_NIU_A 161
  353. #define SRST_VCODEC_H 162
  354. #define SRST_VCODEC_NIU_H 163
  355. #define SRST_VDEC_A 164
  356. #define SRST_VDEC_NIU_A 165
  357. #define SRST_VDEC_H 166
  358. #define SRST_VDEC_NIU_H 167
  359. #define SRST_VDEC_CORE 168
  360. #define SRST_VDEC_CABAC 169
  361. #define SRST_DDRPHYDIV 175
  362. #define SRST_RKVENC_NIU_A 176
  363. #define SRST_RKVENC_NIU_H 177
  364. #define SRST_RKVENC_H265_A 178
  365. #define SRST_RKVENC_H265_P 179
  366. #define SRST_RKVENC_H265_CORE 180
  367. #define SRST_RKVENC_H265_DSP 181
  368. #define SRST_RKVENC_H264_A 182
  369. #define SRST_RKVENC_H264_H 183
  370. #define SRST_RKVENC_INTMEM 184
  371. #endif