rk3288-cru.h 8.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2014 MundoReader S.L.
  4. * Author: Heiko Stuebner <heiko@sntech.de>
  5. */
  6. /* core clocks */
  7. #define PLL_APLL 1
  8. #define PLL_DPLL 2
  9. #define PLL_CPLL 3
  10. #define PLL_GPLL 4
  11. #define PLL_NPLL 5
  12. #define ARMCLK 6
  13. /* sclk gates (special clocks) */
  14. #define SCLK_GPU 64
  15. #define SCLK_SPI0 65
  16. #define SCLK_SPI1 66
  17. #define SCLK_SPI2 67
  18. #define SCLK_SDMMC 68
  19. #define SCLK_SDIO0 69
  20. #define SCLK_SDIO1 70
  21. #define SCLK_EMMC 71
  22. #define SCLK_TSADC 72
  23. #define SCLK_SARADC 73
  24. #define SCLK_PS2C 74
  25. #define SCLK_NANDC0 75
  26. #define SCLK_NANDC1 76
  27. #define SCLK_UART0 77
  28. #define SCLK_UART1 78
  29. #define SCLK_UART2 79
  30. #define SCLK_UART3 80
  31. #define SCLK_UART4 81
  32. #define SCLK_I2S0 82
  33. #define SCLK_SPDIF 83
  34. #define SCLK_SPDIF8CH 84
  35. #define SCLK_TIMER0 85
  36. #define SCLK_TIMER1 86
  37. #define SCLK_TIMER2 87
  38. #define SCLK_TIMER3 88
  39. #define SCLK_TIMER4 89
  40. #define SCLK_TIMER5 90
  41. #define SCLK_TIMER6 91
  42. #define SCLK_HSADC 92
  43. #define SCLK_OTGPHY0 93
  44. #define SCLK_OTGPHY1 94
  45. #define SCLK_OTGPHY2 95
  46. #define SCLK_OTG_ADP 96
  47. #define SCLK_HSICPHY480M 97
  48. #define SCLK_HSICPHY12M 98
  49. #define SCLK_MACREF 99
  50. #define SCLK_LCDC_PWM0 100
  51. #define SCLK_LCDC_PWM1 101
  52. #define SCLK_MAC_RX 102
  53. #define SCLK_MAC_TX 103
  54. #define SCLK_EDP_24M 104
  55. #define SCLK_EDP 105
  56. #define SCLK_RGA 106
  57. #define SCLK_ISP 107
  58. #define SCLK_ISP_JPE 108
  59. #define SCLK_HDMI_HDCP 109
  60. #define SCLK_HDMI_CEC 110
  61. #define SCLK_HEVC_CABAC 111
  62. #define SCLK_HEVC_CORE 112
  63. #define SCLK_I2S0_OUT 113
  64. #define SCLK_SDMMC_DRV 114
  65. #define SCLK_SDIO0_DRV 115
  66. #define SCLK_SDIO1_DRV 116
  67. #define SCLK_EMMC_DRV 117
  68. #define SCLK_SDMMC_SAMPLE 118
  69. #define SCLK_SDIO0_SAMPLE 119
  70. #define SCLK_SDIO1_SAMPLE 120
  71. #define SCLK_EMMC_SAMPLE 121
  72. #define SCLK_USBPHY480M_SRC 122
  73. #define SCLK_PVTM_CORE 123
  74. #define SCLK_PVTM_GPU 124
  75. #define SCLK_MAC_PLL 150
  76. #define SCLK_MAC 151
  77. #define SCLK_MACREF_OUT 152
  78. #define DCLK_VOP0 190
  79. #define DCLK_VOP1 191
  80. /* aclk gates */
  81. #define ACLK_GPU 192
  82. #define ACLK_DMAC1 193
  83. #define ACLK_DMAC2 194
  84. #define ACLK_MMU 195
  85. #define ACLK_GMAC 196
  86. #define ACLK_VOP0 197
  87. #define ACLK_VOP1 198
  88. #define ACLK_CRYPTO 199
  89. #define ACLK_RGA 200
  90. #define ACLK_RGA_NIU 201
  91. #define ACLK_IEP 202
  92. #define ACLK_VIO0_NIU 203
  93. #define ACLK_VIP 204
  94. #define ACLK_ISP 205
  95. #define ACLK_VIO1_NIU 206
  96. #define ACLK_HEVC 207
  97. #define ACLK_VCODEC 208
  98. #define ACLK_CPU 209
  99. #define ACLK_PERI 210
  100. /* pclk gates */
  101. #define PCLK_GPIO0 320
  102. #define PCLK_GPIO1 321
  103. #define PCLK_GPIO2 322
  104. #define PCLK_GPIO3 323
  105. #define PCLK_GPIO4 324
  106. #define PCLK_GPIO5 325
  107. #define PCLK_GPIO6 326
  108. #define PCLK_GPIO7 327
  109. #define PCLK_GPIO8 328
  110. #define PCLK_GRF 329
  111. #define PCLK_SGRF 330
  112. #define PCLK_PMU 331
  113. #define PCLK_I2C0 332
  114. #define PCLK_I2C1 333
  115. #define PCLK_I2C2 334
  116. #define PCLK_I2C3 335
  117. #define PCLK_I2C4 336
  118. #define PCLK_I2C5 337
  119. #define PCLK_SPI0 338
  120. #define PCLK_SPI1 339
  121. #define PCLK_SPI2 340
  122. #define PCLK_UART0 341
  123. #define PCLK_UART1 342
  124. #define PCLK_UART2 343
  125. #define PCLK_UART3 344
  126. #define PCLK_UART4 345
  127. #define PCLK_TSADC 346
  128. #define PCLK_SARADC 347
  129. #define PCLK_SIM 348
  130. #define PCLK_GMAC 349
  131. #define PCLK_PWM 350
  132. #define PCLK_RKPWM 351
  133. #define PCLK_PS2C 352
  134. #define PCLK_TIMER 353
  135. #define PCLK_TZPC 354
  136. #define PCLK_EDP_CTRL 355
  137. #define PCLK_MIPI_DSI0 356
  138. #define PCLK_MIPI_DSI1 357
  139. #define PCLK_MIPI_CSI 358
  140. #define PCLK_LVDS_PHY 359
  141. #define PCLK_HDMI_CTRL 360
  142. #define PCLK_VIO2_H2P 361
  143. #define PCLK_CPU 362
  144. #define PCLK_PERI 363
  145. #define PCLK_DDRUPCTL0 364
  146. #define PCLK_PUBL0 365
  147. #define PCLK_DDRUPCTL1 366
  148. #define PCLK_PUBL1 367
  149. #define PCLK_WDT 368
  150. /* hclk gates */
  151. #define HCLK_GPS 448
  152. #define HCLK_OTG0 449
  153. #define HCLK_USBHOST0 450
  154. #define HCLK_USBHOST1 451
  155. #define HCLK_HSIC 452
  156. #define HCLK_NANDC0 453
  157. #define HCLK_NANDC1 454
  158. #define HCLK_TSP 455
  159. #define HCLK_SDMMC 456
  160. #define HCLK_SDIO0 457
  161. #define HCLK_SDIO1 458
  162. #define HCLK_EMMC 459
  163. #define HCLK_HSADC 460
  164. #define HCLK_CRYPTO 461
  165. #define HCLK_I2S0 462
  166. #define HCLK_SPDIF 463
  167. #define HCLK_SPDIF8CH 464
  168. #define HCLK_VOP0 465
  169. #define HCLK_VOP1 466
  170. #define HCLK_ROM 467
  171. #define HCLK_IEP 468
  172. #define HCLK_ISP 469
  173. #define HCLK_RGA 470
  174. #define HCLK_VIO_AHB_ARBI 471
  175. #define HCLK_VIO_NIU 472
  176. #define HCLK_VIP 473
  177. #define HCLK_VIO2_H2P 474
  178. #define HCLK_HEVC 475
  179. #define HCLK_VCODEC 476
  180. #define HCLK_CPU 477
  181. #define HCLK_PERI 478
  182. #define CLK_NR_CLKS (HCLK_PERI + 1)
  183. /* soft-reset indices */
  184. #define SRST_CORE0 0
  185. #define SRST_CORE1 1
  186. #define SRST_CORE2 2
  187. #define SRST_CORE3 3
  188. #define SRST_CORE0_PO 4
  189. #define SRST_CORE1_PO 5
  190. #define SRST_CORE2_PO 6
  191. #define SRST_CORE3_PO 7
  192. #define SRST_PDCORE_STRSYS 8
  193. #define SRST_PDBUS_STRSYS 9
  194. #define SRST_L2C 10
  195. #define SRST_TOPDBG 11
  196. #define SRST_CORE0_DBG 12
  197. #define SRST_CORE1_DBG 13
  198. #define SRST_CORE2_DBG 14
  199. #define SRST_CORE3_DBG 15
  200. #define SRST_PDBUG_AHB_ARBITOR 16
  201. #define SRST_EFUSE256 17
  202. #define SRST_DMAC1 18
  203. #define SRST_INTMEM 19
  204. #define SRST_ROM 20
  205. #define SRST_SPDIF8CH 21
  206. #define SRST_TIMER 22
  207. #define SRST_I2S0 23
  208. #define SRST_SPDIF 24
  209. #define SRST_TIMER0 25
  210. #define SRST_TIMER1 26
  211. #define SRST_TIMER2 27
  212. #define SRST_TIMER3 28
  213. #define SRST_TIMER4 29
  214. #define SRST_TIMER5 30
  215. #define SRST_EFUSE 31
  216. #define SRST_GPIO0 32
  217. #define SRST_GPIO1 33
  218. #define SRST_GPIO2 34
  219. #define SRST_GPIO3 35
  220. #define SRST_GPIO4 36
  221. #define SRST_GPIO5 37
  222. #define SRST_GPIO6 38
  223. #define SRST_GPIO7 39
  224. #define SRST_GPIO8 40
  225. #define SRST_I2C0 42
  226. #define SRST_I2C1 43
  227. #define SRST_I2C2 44
  228. #define SRST_I2C3 45
  229. #define SRST_I2C4 46
  230. #define SRST_I2C5 47
  231. #define SRST_DWPWM 48
  232. #define SRST_MMC_PERI 49
  233. #define SRST_PERIPH_MMU 50
  234. #define SRST_DAP 51
  235. #define SRST_DAP_SYS 52
  236. #define SRST_TPIU 53
  237. #define SRST_PMU_APB 54
  238. #define SRST_GRF 55
  239. #define SRST_PMU 56
  240. #define SRST_PERIPH_AXI 57
  241. #define SRST_PERIPH_AHB 58
  242. #define SRST_PERIPH_APB 59
  243. #define SRST_PERIPH_NIU 60
  244. #define SRST_PDPERI_AHB_ARBI 61
  245. #define SRST_EMEM 62
  246. #define SRST_USB_PERI 63
  247. #define SRST_DMAC2 64
  248. #define SRST_MAC 66
  249. #define SRST_GPS 67
  250. #define SRST_RKPWM 69
  251. #define SRST_CCP 71
  252. #define SRST_USBHOST0 72
  253. #define SRST_HSIC 73
  254. #define SRST_HSIC_AUX 74
  255. #define SRST_HSIC_PHY 75
  256. #define SRST_HSADC 76
  257. #define SRST_NANDC0 77
  258. #define SRST_NANDC1 78
  259. #define SRST_TZPC 80
  260. #define SRST_SPI0 83
  261. #define SRST_SPI1 84
  262. #define SRST_SPI2 85
  263. #define SRST_SARADC 87
  264. #define SRST_PDALIVE_NIU 88
  265. #define SRST_PDPMU_INTMEM 89
  266. #define SRST_PDPMU_NIU 90
  267. #define SRST_SGRF 91
  268. #define SRST_VIO_ARBI 96
  269. #define SRST_RGA_NIU 97
  270. #define SRST_VIO0_NIU_AXI 98
  271. #define SRST_VIO_NIU_AHB 99
  272. #define SRST_LCDC0_AXI 100
  273. #define SRST_LCDC0_AHB 101
  274. #define SRST_LCDC0_DCLK 102
  275. #define SRST_VIO1_NIU_AXI 103
  276. #define SRST_VIP 104
  277. #define SRST_RGA_CORE 105
  278. #define SRST_IEP_AXI 106
  279. #define SRST_IEP_AHB 107
  280. #define SRST_RGA_AXI 108
  281. #define SRST_RGA_AHB 109
  282. #define SRST_ISP 110
  283. #define SRST_EDP 111
  284. #define SRST_VCODEC_AXI 112
  285. #define SRST_VCODEC_AHB 113
  286. #define SRST_VIO_H2P 114
  287. #define SRST_MIPIDSI0 115
  288. #define SRST_MIPIDSI1 116
  289. #define SRST_MIPICSI 117
  290. #define SRST_LVDS_PHY 118
  291. #define SRST_LVDS_CON 119
  292. #define SRST_GPU 120
  293. #define SRST_HDMI 121
  294. #define SRST_CORE_PVTM 124
  295. #define SRST_GPU_PVTM 125
  296. #define SRST_MMC0 128
  297. #define SRST_SDIO0 129
  298. #define SRST_SDIO1 130
  299. #define SRST_EMMC 131
  300. #define SRST_USBOTG_AHB 132
  301. #define SRST_USBOTG_PHY 133
  302. #define SRST_USBOTG_CON 134
  303. #define SRST_USBHOST0_AHB 135
  304. #define SRST_USBHOST0_PHY 136
  305. #define SRST_USBHOST0_CON 137
  306. #define SRST_USBHOST1_AHB 138
  307. #define SRST_USBHOST1_PHY 139
  308. #define SRST_USBHOST1_CON 140
  309. #define SRST_USB_ADP 141
  310. #define SRST_ACC_EFUSE 142
  311. #define SRST_CORESIGHT 144
  312. #define SRST_PD_CORE_AHB_NOC 145
  313. #define SRST_PD_CORE_APB_NOC 146
  314. #define SRST_PD_CORE_MP_AXI 147
  315. #define SRST_GIC 148
  316. #define SRST_LCDC_PWM0 149
  317. #define SRST_LCDC_PWM1 150
  318. #define SRST_VIO0_H2P_BRG 151
  319. #define SRST_VIO1_H2P_BRG 152
  320. #define SRST_RGA_H2P_BRG 153
  321. #define SRST_HEVC 154
  322. #define SRST_TSADC 159
  323. #define SRST_DDRPHY0 160
  324. #define SRST_DDRPHY0_APB 161
  325. #define SRST_DDRCTRL0 162
  326. #define SRST_DDRCTRL0_APB 163
  327. #define SRST_DDRPHY0_CTRL 164
  328. #define SRST_DDRPHY1 165
  329. #define SRST_DDRPHY1_APB 166
  330. #define SRST_DDRCTRL1 167
  331. #define SRST_DDRCTRL1_APB 168
  332. #define SRST_DDRPHY1_CTRL 169
  333. #define SRST_DDRMSCH0 170
  334. #define SRST_DDRMSCH1 171
  335. #define SRST_CRYPTO 174
  336. #define SRST_C2C_HOST 175
  337. #define SRST_LCDC1_AXI 176
  338. #define SRST_LCDC1_AHB 177
  339. #define SRST_LCDC1_DCLK 178
  340. #define SRST_UART0 179
  341. #define SRST_UART1 180
  342. #define SRST_UART2 181
  343. #define SRST_UART3 182
  344. #define SRST_UART4 183
  345. #define SRST_SIMC 186
  346. #define SRST_PS2C 187
  347. #define SRST_TSP 188
  348. #define SRST_TSP_CLKIN0 189
  349. #define SRST_TSP_CLKIN1 190
  350. #define SRST_TSP_27M 191