r8a7796-cpg-mssr.h 1.8 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465
  1. /* SPDX-License-Identifier: GPL-2.0+
  2. *
  3. * Copyright (C) 2016 Renesas Electronics Corp.
  4. */
  5. #ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
  6. #define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
  7. #include <dt-bindings/clock/renesas-cpg-mssr.h>
  8. /* r8a7796 CPG Core Clocks */
  9. #define R8A7796_CLK_Z 0
  10. #define R8A7796_CLK_Z2 1
  11. #define R8A7796_CLK_ZR 2
  12. #define R8A7796_CLK_ZG 3
  13. #define R8A7796_CLK_ZTR 4
  14. #define R8A7796_CLK_ZTRD2 5
  15. #define R8A7796_CLK_ZT 6
  16. #define R8A7796_CLK_ZX 7
  17. #define R8A7796_CLK_S0D1 8
  18. #define R8A7796_CLK_S0D2 9
  19. #define R8A7796_CLK_S0D3 10
  20. #define R8A7796_CLK_S0D4 11
  21. #define R8A7796_CLK_S0D6 12
  22. #define R8A7796_CLK_S0D8 13
  23. #define R8A7796_CLK_S0D12 14
  24. #define R8A7796_CLK_S1D1 15
  25. #define R8A7796_CLK_S1D2 16
  26. #define R8A7796_CLK_S1D4 17
  27. #define R8A7796_CLK_S2D1 18
  28. #define R8A7796_CLK_S2D2 19
  29. #define R8A7796_CLK_S2D4 20
  30. #define R8A7796_CLK_S3D1 21
  31. #define R8A7796_CLK_S3D2 22
  32. #define R8A7796_CLK_S3D4 23
  33. #define R8A7796_CLK_LB 24
  34. #define R8A7796_CLK_CL 25
  35. #define R8A7796_CLK_ZB3 26
  36. #define R8A7796_CLK_ZB3D2 27
  37. #define R8A7796_CLK_ZB3D4 28
  38. #define R8A7796_CLK_CR 29
  39. #define R8A7796_CLK_CRD2 30
  40. #define R8A7796_CLK_SD0H 31
  41. #define R8A7796_CLK_SD0 32
  42. #define R8A7796_CLK_SD1H 33
  43. #define R8A7796_CLK_SD1 34
  44. #define R8A7796_CLK_SD2H 35
  45. #define R8A7796_CLK_SD2 36
  46. #define R8A7796_CLK_SD3H 37
  47. #define R8A7796_CLK_SD3 38
  48. #define R8A7796_CLK_SSP2 39
  49. #define R8A7796_CLK_SSP1 40
  50. #define R8A7796_CLK_SSPRS 41
  51. #define R8A7796_CLK_RPC 42
  52. #define R8A7796_CLK_RPCD2 43
  53. #define R8A7796_CLK_MSO 44
  54. #define R8A7796_CLK_CANFD 45
  55. #define R8A7796_CLK_HDMI 46
  56. #define R8A7796_CLK_CSI0 47
  57. /* CLK_CSIREF was removed */
  58. #define R8A7796_CLK_CP 49
  59. #define R8A7796_CLK_CPEX 50
  60. #define R8A7796_CLK_R 51
  61. #define R8A7796_CLK_OSC 52
  62. #endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */