r7s72100-clock.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2014 Renesas Solutions Corp.
  4. * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
  5. */
  6. #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
  7. #define __DT_BINDINGS_CLOCK_R7S72100_H__
  8. #define R7S72100_CLK_PLL 0
  9. #define R7S72100_CLK_I 1
  10. #define R7S72100_CLK_G 2
  11. /* MSTP2 */
  12. #define R7S72100_CLK_CORESIGHT 0
  13. /* MSTP3 */
  14. #define R7S72100_CLK_IEBUS 7
  15. #define R7S72100_CLK_IRDA 6
  16. #define R7S72100_CLK_LIN0 5
  17. #define R7S72100_CLK_LIN1 4
  18. #define R7S72100_CLK_MTU2 3
  19. #define R7S72100_CLK_CAN 2
  20. #define R7S72100_CLK_ADCPWR 1
  21. #define R7S72100_CLK_PWM 0
  22. /* MSTP4 */
  23. #define R7S72100_CLK_SCIF0 7
  24. #define R7S72100_CLK_SCIF1 6
  25. #define R7S72100_CLK_SCIF2 5
  26. #define R7S72100_CLK_SCIF3 4
  27. #define R7S72100_CLK_SCIF4 3
  28. #define R7S72100_CLK_SCIF5 2
  29. #define R7S72100_CLK_SCIF6 1
  30. #define R7S72100_CLK_SCIF7 0
  31. /* MSTP5 */
  32. #define R7S72100_CLK_SCI0 7
  33. #define R7S72100_CLK_SCI1 6
  34. #define R7S72100_CLK_SG0 5
  35. #define R7S72100_CLK_SG1 4
  36. #define R7S72100_CLK_SG2 3
  37. #define R7S72100_CLK_SG3 2
  38. #define R7S72100_CLK_OSTM0 1
  39. #define R7S72100_CLK_OSTM1 0
  40. /* MSTP6 */
  41. #define R7S72100_CLK_ADC 7
  42. #define R7S72100_CLK_CEU 6
  43. #define R7S72100_CLK_DOC0 5
  44. #define R7S72100_CLK_DOC1 4
  45. #define R7S72100_CLK_DRC0 3
  46. #define R7S72100_CLK_DRC1 2
  47. #define R7S72100_CLK_JCU 1
  48. #define R7S72100_CLK_RTC 0
  49. /* MSTP7 */
  50. #define R7S72100_CLK_VDEC0 7
  51. #define R7S72100_CLK_VDEC1 6
  52. #define R7S72100_CLK_ETHER 4
  53. #define R7S72100_CLK_NAND 3
  54. #define R7S72100_CLK_USB0 1
  55. #define R7S72100_CLK_USB1 0
  56. /* MSTP8 */
  57. #define R7S72100_CLK_IMR0 7
  58. #define R7S72100_CLK_IMR1 6
  59. #define R7S72100_CLK_IMRDISP 5
  60. #define R7S72100_CLK_MMCIF 4
  61. #define R7S72100_CLK_MLB 3
  62. #define R7S72100_CLK_ETHAVB 2
  63. #define R7S72100_CLK_SCUX 1
  64. /* MSTP9 */
  65. #define R7S72100_CLK_I2C0 7
  66. #define R7S72100_CLK_I2C1 6
  67. #define R7S72100_CLK_I2C2 5
  68. #define R7S72100_CLK_I2C3 4
  69. #define R7S72100_CLK_SPIBSC0 3
  70. #define R7S72100_CLK_SPIBSC1 2
  71. #define R7S72100_CLK_VDC50 1 /* and LVDS */
  72. #define R7S72100_CLK_VDC51 0
  73. /* MSTP10 */
  74. #define R7S72100_CLK_SPI0 7
  75. #define R7S72100_CLK_SPI1 6
  76. #define R7S72100_CLK_SPI2 5
  77. #define R7S72100_CLK_SPI3 4
  78. #define R7S72100_CLK_SPI4 3
  79. #define R7S72100_CLK_CDROM 2
  80. #define R7S72100_CLK_SPDIF 1
  81. #define R7S72100_CLK_RGPVG2 0
  82. /* MSTP11 */
  83. #define R7S72100_CLK_SSI0 5
  84. #define R7S72100_CLK_SSI1 4
  85. #define R7S72100_CLK_SSI2 3
  86. #define R7S72100_CLK_SSI3 2
  87. #define R7S72100_CLK_SSI4 1
  88. #define R7S72100_CLK_SSI5 0
  89. /* MSTP12 */
  90. #define R7S72100_CLK_SDHI00 3
  91. #define R7S72100_CLK_SDHI01 2
  92. #define R7S72100_CLK_SDHI10 1
  93. #define R7S72100_CLK_SDHI11 0
  94. /* MSTP13 */
  95. #define R7S72100_CLK_PIX1 2
  96. #define R7S72100_CLK_PIX0 1
  97. #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */