px30-cru.h 8.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
  4. * Author: Elaine <zhangqing@rock-chips.com>
  5. */
  6. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
  7. #define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
  8. /* core clocks */
  9. #define PLL_APLL 1
  10. #define PLL_DPLL 2
  11. #define PLL_CPLL 3
  12. #define PLL_NPLL 4
  13. #define APLL_BOOST_H 5
  14. #define APLL_BOOST_L 6
  15. #define ARMCLK 7
  16. /* sclk gates (special clocks) */
  17. #define USB480M 14
  18. #define SCLK_PDM 15
  19. #define SCLK_I2S0_TX 16
  20. #define SCLK_I2S0_TX_OUT 17
  21. #define SCLK_I2S0_RX 18
  22. #define SCLK_I2S0_RX_OUT 19
  23. #define SCLK_I2S1 20
  24. #define SCLK_I2S1_OUT 21
  25. #define SCLK_I2S2 22
  26. #define SCLK_I2S2_OUT 23
  27. #define SCLK_UART1 24
  28. #define SCLK_UART2 25
  29. #define SCLK_UART3 26
  30. #define SCLK_UART4 27
  31. #define SCLK_UART5 28
  32. #define SCLK_I2C0 29
  33. #define SCLK_I2C1 30
  34. #define SCLK_I2C2 31
  35. #define SCLK_I2C3 32
  36. #define SCLK_I2C4 33
  37. #define SCLK_PWM0 34
  38. #define SCLK_PWM1 35
  39. #define SCLK_SPI0 36
  40. #define SCLK_SPI1 37
  41. #define SCLK_TIMER0 38
  42. #define SCLK_TIMER1 39
  43. #define SCLK_TIMER2 40
  44. #define SCLK_TIMER3 41
  45. #define SCLK_TIMER4 42
  46. #define SCLK_TIMER5 43
  47. #define SCLK_TSADC 44
  48. #define SCLK_SARADC 45
  49. #define SCLK_OTP 46
  50. #define SCLK_OTP_USR 47
  51. #define SCLK_CRYPTO 48
  52. #define SCLK_CRYPTO_APK 49
  53. #define SCLK_DDRC 50
  54. #define SCLK_ISP 51
  55. #define SCLK_CIF_OUT 52
  56. #define SCLK_RGA_CORE 53
  57. #define SCLK_VOPB_PWM 54
  58. #define SCLK_NANDC 55
  59. #define SCLK_SDIO 56
  60. #define SCLK_EMMC 57
  61. #define SCLK_SFC 58
  62. #define SCLK_SDMMC 59
  63. #define SCLK_OTG_ADP 60
  64. #define SCLK_GMAC_SRC 61
  65. #define SCLK_GMAC 62
  66. #define SCLK_GMAC_RX_TX 63
  67. #define SCLK_MAC_REF 64
  68. #define SCLK_MAC_REFOUT 65
  69. #define SCLK_MAC_OUT 66
  70. #define SCLK_SDMMC_DRV 67
  71. #define SCLK_SDMMC_SAMPLE 68
  72. #define SCLK_SDIO_DRV 69
  73. #define SCLK_SDIO_SAMPLE 70
  74. #define SCLK_EMMC_DRV 71
  75. #define SCLK_EMMC_SAMPLE 72
  76. #define SCLK_GPU 73
  77. #define SCLK_PVTM 74
  78. #define SCLK_CORE_VPU 75
  79. #define SCLK_GMAC_RMII 76
  80. #define SCLK_UART2_SRC 77
  81. #define SCLK_NANDC_DIV 78
  82. #define SCLK_NANDC_DIV50 79
  83. #define SCLK_SDIO_DIV 80
  84. #define SCLK_SDIO_DIV50 81
  85. #define SCLK_EMMC_DIV 82
  86. #define SCLK_EMMC_DIV50 83
  87. /* dclk gates */
  88. #define DCLK_VOPB 150
  89. #define DCLK_VOPL 151
  90. /* aclk gates */
  91. #define ACLK_GPU 170
  92. #define ACLK_BUS_PRE 171
  93. #define ACLK_CRYPTO 172
  94. #define ACLK_VI_PRE 173
  95. #define ACLK_VO_PRE 174
  96. #define ACLK_VPU 175
  97. #define ACLK_PERI_PRE 176
  98. #define ACLK_GMAC 178
  99. #define ACLK_CIF 179
  100. #define ACLK_ISP 180
  101. #define ACLK_VOPB 181
  102. #define ACLK_VOPL 182
  103. #define ACLK_RGA 183
  104. #define ACLK_GIC 184
  105. #define ACLK_DCF 186
  106. #define ACLK_DMAC 187
  107. /* hclk gates */
  108. #define HCLK_BUS_PRE 240
  109. #define HCLK_CRYPTO 241
  110. #define HCLK_VI_PRE 242
  111. #define HCLK_VO_PRE 243
  112. #define HCLK_VPU 244
  113. #define HCLK_PERI_PRE 245
  114. #define HCLK_MMC_NAND 246
  115. #define HCLK_SDMMC 247
  116. #define HCLK_USB 248
  117. #define HCLK_CIF 249
  118. #define HCLK_ISP 250
  119. #define HCLK_VOPB 251
  120. #define HCLK_VOPL 252
  121. #define HCLK_RGA 253
  122. #define HCLK_NANDC 254
  123. #define HCLK_SDIO 255
  124. #define HCLK_EMMC 256
  125. #define HCLK_SFC 257
  126. #define HCLK_OTG 258
  127. #define HCLK_HOST 259
  128. #define HCLK_HOST_ARB 260
  129. #define HCLK_PDM 261
  130. #define HCLK_I2S0 262
  131. #define HCLK_I2S1 263
  132. #define HCLK_I2S2 264
  133. /* pclk gates */
  134. #define PCLK_BUS_PRE 320
  135. #define PCLK_DDR 321
  136. #define PCLK_VO_PRE 322
  137. #define PCLK_GMAC 323
  138. #define PCLK_MIPI_DSI 324
  139. #define PCLK_MIPIDSIPHY 325
  140. #define PCLK_MIPICSIPHY 326
  141. #define PCLK_USB_GRF 327
  142. #define PCLK_DCF 328
  143. #define PCLK_UART1 329
  144. #define PCLK_UART2 330
  145. #define PCLK_UART3 331
  146. #define PCLK_UART4 332
  147. #define PCLK_UART5 333
  148. #define PCLK_I2C0 334
  149. #define PCLK_I2C1 335
  150. #define PCLK_I2C2 336
  151. #define PCLK_I2C3 337
  152. #define PCLK_I2C4 338
  153. #define PCLK_PWM0 339
  154. #define PCLK_PWM1 340
  155. #define PCLK_SPI0 341
  156. #define PCLK_SPI1 342
  157. #define PCLK_SARADC 343
  158. #define PCLK_TSADC 344
  159. #define PCLK_TIMER 345
  160. #define PCLK_OTP_NS 346
  161. #define PCLK_WDT_NS 347
  162. #define PCLK_GPIO1 348
  163. #define PCLK_GPIO2 349
  164. #define PCLK_GPIO3 350
  165. #define PCLK_ISP 351
  166. #define PCLK_CIF 352
  167. #define PCLK_OTP_PHY 353
  168. #define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
  169. /* pmu-clocks indices */
  170. #define PLL_GPLL 1
  171. #define SCLK_RTC32K_PMU 4
  172. #define SCLK_WIFI_PMU 5
  173. #define SCLK_UART0_PMU 6
  174. #define SCLK_PVTM_PMU 7
  175. #define PCLK_PMU_PRE 8
  176. #define SCLK_REF24M_PMU 9
  177. #define SCLK_USBPHY_REF 10
  178. #define SCLK_MIPIDSIPHY_REF 11
  179. #define XIN24M_DIV 12
  180. #define PCLK_GPIO0_PMU 20
  181. #define PCLK_UART0_PMU 21
  182. #define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
  183. /* soft-reset indices */
  184. #define SRST_CORE0_PO 0
  185. #define SRST_CORE1_PO 1
  186. #define SRST_CORE2_PO 2
  187. #define SRST_CORE3_PO 3
  188. #define SRST_CORE0 4
  189. #define SRST_CORE1 5
  190. #define SRST_CORE2 6
  191. #define SRST_CORE3 7
  192. #define SRST_CORE0_DBG 8
  193. #define SRST_CORE1_DBG 9
  194. #define SRST_CORE2_DBG 10
  195. #define SRST_CORE3_DBG 11
  196. #define SRST_TOPDBG 12
  197. #define SRST_CORE_NOC 13
  198. #define SRST_STRC_A 14
  199. #define SRST_L2C 15
  200. #define SRST_DAP 16
  201. #define SRST_CORE_PVTM 17
  202. #define SRST_GPU 18
  203. #define SRST_GPU_NIU 19
  204. #define SRST_UPCTL2 20
  205. #define SRST_UPCTL2_A 21
  206. #define SRST_UPCTL2_P 22
  207. #define SRST_MSCH 23
  208. #define SRST_MSCH_P 24
  209. #define SRST_DDRMON_P 25
  210. #define SRST_DDRSTDBY_P 26
  211. #define SRST_DDRSTDBY 27
  212. #define SRST_DDRGRF_p 28
  213. #define SRST_AXI_SPLIT_A 29
  214. #define SRST_AXI_CMD_A 30
  215. #define SRST_AXI_CMD_P 31
  216. #define SRST_DDRPHY 32
  217. #define SRST_DDRPHYDIV 33
  218. #define SRST_DDRPHY_P 34
  219. #define SRST_VPU_A 36
  220. #define SRST_VPU_NIU_A 37
  221. #define SRST_VPU_H 38
  222. #define SRST_VPU_NIU_H 39
  223. #define SRST_VI_NIU_A 40
  224. #define SRST_VI_NIU_H 41
  225. #define SRST_ISP_H 42
  226. #define SRST_ISP 43
  227. #define SRST_CIF_A 44
  228. #define SRST_CIF_H 45
  229. #define SRST_CIF_PCLKIN 46
  230. #define SRST_MIPICSIPHY_P 47
  231. #define SRST_VO_NIU_A 48
  232. #define SRST_VO_NIU_H 49
  233. #define SRST_VO_NIU_P 50
  234. #define SRST_VOPB_A 51
  235. #define SRST_VOPB_H 52
  236. #define SRST_VOPB 53
  237. #define SRST_PWM_VOPB 54
  238. #define SRST_VOPL_A 55
  239. #define SRST_VOPL_H 56
  240. #define SRST_VOPL 57
  241. #define SRST_RGA_A 58
  242. #define SRST_RGA_H 59
  243. #define SRST_RGA 60
  244. #define SRST_MIPIDSI_HOST_P 61
  245. #define SRST_MIPIDSIPHY_P 62
  246. #define SRST_VPU_CORE 63
  247. #define SRST_PERI_NIU_A 64
  248. #define SRST_USB_NIU_H 65
  249. #define SRST_USB2OTG_H 66
  250. #define SRST_USB2OTG 67
  251. #define SRST_USB2OTG_ADP 68
  252. #define SRST_USB2HOST_H 69
  253. #define SRST_USB2HOST_ARB_H 70
  254. #define SRST_USB2HOST_AUX_H 71
  255. #define SRST_USB2HOST_EHCI 72
  256. #define SRST_USB2HOST 73
  257. #define SRST_USBPHYPOR 74
  258. #define SRST_USBPHY_OTG_PORT 75
  259. #define SRST_USBPHY_HOST_PORT 76
  260. #define SRST_USBPHY_GRF 77
  261. #define SRST_CPU_BOOST_P 78
  262. #define SRST_CPU_BOOST 79
  263. #define SRST_MMC_NAND_NIU_H 80
  264. #define SRST_SDIO_H 81
  265. #define SRST_EMMC_H 82
  266. #define SRST_SFC_H 83
  267. #define SRST_SFC 84
  268. #define SRST_SDCARD_NIU_H 85
  269. #define SRST_SDMMC_H 86
  270. #define SRST_NANDC_H 89
  271. #define SRST_NANDC 90
  272. #define SRST_GMAC_NIU_A 92
  273. #define SRST_GMAC_NIU_P 93
  274. #define SRST_GMAC_A 94
  275. #define SRST_PMU_NIU_P 96
  276. #define SRST_PMU_SGRF_P 97
  277. #define SRST_PMU_GRF_P 98
  278. #define SRST_PMU 99
  279. #define SRST_PMU_MEM_P 100
  280. #define SRST_PMU_GPIO0_P 101
  281. #define SRST_PMU_UART0_P 102
  282. #define SRST_PMU_CRU_P 103
  283. #define SRST_PMU_PVTM 104
  284. #define SRST_PMU_UART 105
  285. #define SRST_PMU_NIU_H 106
  286. #define SRST_PMU_DDR_FAIL_SAVE 107
  287. #define SRST_PMU_CORE_PERF_A 108
  288. #define SRST_PMU_CORE_GRF_P 109
  289. #define SRST_PMU_GPU_PERF_A 110
  290. #define SRST_PMU_GPU_GRF_P 111
  291. #define SRST_CRYPTO_NIU_A 112
  292. #define SRST_CRYPTO_NIU_H 113
  293. #define SRST_CRYPTO_A 114
  294. #define SRST_CRYPTO_H 115
  295. #define SRST_CRYPTO 116
  296. #define SRST_CRYPTO_APK 117
  297. #define SRST_BUS_NIU_H 120
  298. #define SRST_USB_NIU_P 121
  299. #define SRST_BUS_TOP_NIU_P 122
  300. #define SRST_INTMEM_A 123
  301. #define SRST_GIC_A 124
  302. #define SRST_ROM_H 126
  303. #define SRST_DCF_A 127
  304. #define SRST_DCF_P 128
  305. #define SRST_PDM_H 129
  306. #define SRST_PDM 130
  307. #define SRST_I2S0_H 131
  308. #define SRST_I2S0_TX 132
  309. #define SRST_I2S1_H 133
  310. #define SRST_I2S1 134
  311. #define SRST_I2S2_H 135
  312. #define SRST_I2S2 136
  313. #define SRST_UART1_P 137
  314. #define SRST_UART1 138
  315. #define SRST_UART2_P 139
  316. #define SRST_UART2 140
  317. #define SRST_UART3_P 141
  318. #define SRST_UART3 142
  319. #define SRST_UART4_P 143
  320. #define SRST_UART4 144
  321. #define SRST_UART5_P 145
  322. #define SRST_UART5 146
  323. #define SRST_I2C0_P 147
  324. #define SRST_I2C0 148
  325. #define SRST_I2C1_P 149
  326. #define SRST_I2C1 150
  327. #define SRST_I2C2_P 151
  328. #define SRST_I2C2 152
  329. #define SRST_I2C3_P 153
  330. #define SRST_I2C3 154
  331. #define SRST_PWM0_P 157
  332. #define SRST_PWM0 158
  333. #define SRST_PWM1_P 159
  334. #define SRST_PWM1 160
  335. #define SRST_SPI0_P 161
  336. #define SRST_SPI0 162
  337. #define SRST_SPI1_P 163
  338. #define SRST_SPI1 164
  339. #define SRST_SARADC_P 165
  340. #define SRST_SARADC 166
  341. #define SRST_TSADC_P 167
  342. #define SRST_TSADC 168
  343. #define SRST_TIMER_P 169
  344. #define SRST_TIMER0 170
  345. #define SRST_TIMER1 171
  346. #define SRST_TIMER2 172
  347. #define SRST_TIMER3 173
  348. #define SRST_TIMER4 174
  349. #define SRST_TIMER5 175
  350. #define SRST_OTP_NS_P 176
  351. #define SRST_OTP_NS_SBPI 177
  352. #define SRST_OTP_NS_USR 178
  353. #define SRST_OTP_PHY_P 179
  354. #define SRST_OTP_PHY 180
  355. #define SRST_WDT_NS_P 181
  356. #define SRST_GPIO1_P 182
  357. #define SRST_GPIO2_P 183
  358. #define SRST_GPIO3_P 184
  359. #define SRST_SGRF_P 185
  360. #define SRST_GRF_P 186
  361. #define SRST_I2S0_RX 191
  362. #endif