dp83848.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * DP83848 ethernet Physical layer
  4. *
  5. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6. *
  7. */
  8. /* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
  9. #define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
  10. #define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
  11. #define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
  12. #define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
  13. #define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
  14. #define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
  15. #define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
  16. #define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
  17. #define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
  18. #define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
  19. /*--Bit definitions: DP83848_CTL_REG */
  20. #define DP83848_RESET (1 << 15) /* 1= S/W Reset */
  21. #define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
  22. #define DP83848_SPEED_SELECT (1 << 13)
  23. #define DP83848_AUTONEG (1 << 12)
  24. #define DP83848_POWER_DOWN (1 << 11)
  25. #define DP83848_ISOLATE (1 << 10)
  26. #define DP83848_RESTART_AUTONEG (1 << 9)
  27. #define DP83848_DUPLEX_MODE (1 << 8)
  28. #define DP83848_COLLISION_TEST (1 << 7)
  29. /*--Bit definitions: DP83848_STAT_REG */
  30. #define DP83848_100BASE_T4 (1 << 15)
  31. #define DP83848_100BASE_TX_FD (1 << 14)
  32. #define DP83848_100BASE_TX_HD (1 << 13)
  33. #define DP83848_10BASE_T_FD (1 << 12)
  34. #define DP83848_10BASE_T_HD (1 << 11)
  35. #define DP83848_MF_PREAMB_SUPPR (1 << 6)
  36. #define DP83848_AUTONEG_COMP (1 << 5)
  37. #define DP83848_RMT_FAULT (1 << 4)
  38. #define DP83848_AUTONEG_ABILITY (1 << 3)
  39. #define DP83848_LINK_STATUS (1 << 2)
  40. #define DP83848_JABBER_DETECT (1 << 1)
  41. #define DP83848_EXTEND_CAPAB (1 << 0)
  42. /*--definitions: DP83848_PHYID1 */
  43. #define DP83848_PHYID1_OUI 0x2000
  44. #define DP83848_PHYID2_OUI 0x5c90
  45. /*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
  46. #define DP83848_NP (1 << 15)
  47. #define DP83848_ACK (1 << 14)
  48. #define DP83848_RF (1 << 13)
  49. #define DP83848_PAUSE (1 << 10)
  50. #define DP83848_T4 (1 << 9)
  51. #define DP83848_TX_FDX (1 << 8)
  52. #define DP83848_TX_HDX (1 << 7)
  53. #define DP83848_10_FDX (1 << 6)
  54. #define DP83848_10_HDX (1 << 5)
  55. #define DP83848_AN_IEEE_802_3 0x0001
  56. /*--Bit definitions: DP83848_ANER */
  57. #define DP83848_PDF (1 << 4)
  58. #define DP83848_LP_NP_ABLE (1 << 3)
  59. #define DP83848_NP_ABLE (1 << 2)
  60. #define DP83848_PAGE_RX (1 << 1)
  61. #define DP83848_LP_AN_ABLE (1 << 0)
  62. /*--Bit definitions: DP83848_PHY_STAT */
  63. #define DP83848_RX_ERR_LATCH (1 << 13)
  64. #define DP83848_POLARITY_STAT (1 << 12)
  65. #define DP83848_FALSE_CAR_SENSE (1 << 11)
  66. #define DP83848_SIG_DETECT (1 << 10)
  67. #define DP83848_DESCRAM_LOCK (1 << 9)
  68. #define DP83848_PAGE_RCV (1 << 8)
  69. #define DP83848_PHY_RMT_FAULT (1 << 6)
  70. #define DP83848_JABBER (1 << 5)
  71. #define DP83848_AUTONEG_COMPLETE (1 << 4)
  72. #define DP83848_LOOPBACK_STAT (1 << 3)
  73. #define DP83848_DUPLEX (1 << 2)
  74. #define DP83848_SPEED (1 << 1)
  75. #define DP83848_LINK (1 << 0)