serial_sh.h 724 B

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  4. * Copyright (c) 2014 Renesas Electronics Corporation
  5. */
  6. #ifndef __serial_sh_h
  7. #define __serial_sh_h
  8. enum sh_clk_mode {
  9. INT_CLK,
  10. EXT_CLK,
  11. };
  12. enum sh_serial_type {
  13. PORT_SCI,
  14. PORT_SCIF,
  15. PORT_SCIFA,
  16. PORT_SCIFB,
  17. };
  18. /*
  19. * Information about SCIF port
  20. *
  21. * @base: Register base address
  22. * @clk: Input clock rate, used for calculating the baud rate divisor
  23. * @clk_mode: Clock mode, set internal (INT) or external (EXT)
  24. * @type: Type of SCIF
  25. */
  26. struct sh_serial_platdata {
  27. unsigned long base;
  28. unsigned int clk;
  29. enum sh_clk_mode clk_mode;
  30. enum sh_serial_type type;
  31. };
  32. #endif /* __serial_sh_h */