ddr_spd.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef _DDR_SPD_H_
  6. #define _DDR_SPD_H_
  7. /*
  8. * Format from "JEDEC Standard No. 21-C,
  9. * Appendix D: Rev 1.0: SPD's for DDR SDRAM
  10. */
  11. typedef struct ddr1_spd_eeprom_s {
  12. unsigned char info_size; /* 0 # bytes written into serial memory */
  13. unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
  14. unsigned char mem_type; /* 2 Fundamental memory type */
  15. unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
  16. unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
  17. unsigned char nrows; /* 5 Number of DIMM Banks */
  18. unsigned char dataw_lsb; /* 6 Data Width of this assembly */
  19. unsigned char dataw_msb; /* 7 ... Data Width continuation */
  20. unsigned char voltage; /* 8 Voltage intf std of this assembly */
  21. unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */
  22. unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */
  23. unsigned char config; /* 11 DIMM Configuration type */
  24. unsigned char refresh; /* 12 Refresh Rate/Type */
  25. unsigned char primw; /* 13 Primary SDRAM Width */
  26. unsigned char ecw; /* 14 Error Checking SDRAM width */
  27. unsigned char min_delay; /* 15 for Back to Back Random Address */
  28. unsigned char burstl; /* 16 Burst Lengths Supported */
  29. unsigned char nbanks; /* 17 # of Banks on SDRAM Device */
  30. unsigned char cas_lat; /* 18 CAS# Latencies Supported */
  31. unsigned char cs_lat; /* 19 CS# Latency */
  32. unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */
  33. unsigned char mod_attr; /* 21 SDRAM Module Attributes */
  34. unsigned char dev_attr; /* 22 SDRAM Device Attributes */
  35. unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
  36. unsigned char clk_access2; /* 24 SDRAM Access from
  37. Clk @ CL=X-0.5 (tAC) */
  38. unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
  39. unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
  40. unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
  41. unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
  42. unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
  43. unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
  44. unsigned char bank_dens; /* 31 Density of each bank on module */
  45. unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */
  46. unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */
  47. unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */
  48. unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */
  49. unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
  50. unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
  51. unsigned char trfc; /* 42 Min Auto to Active period tRFC */
  52. unsigned char tckmax; /* 43 Max device cycle time tCKmax */
  53. unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
  54. unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */
  55. unsigned char res_46; /* 46 Reserved */
  56. unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
  57. unsigned char res_48_61[14]; /* 48-61 Reserved */
  58. unsigned char spd_rev; /* 62 SPD Data Revision Code */
  59. unsigned char cksum; /* 63 Checksum for bytes 0-62 */
  60. unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */
  61. unsigned char mloc; /* 72 Manufacturing Location */
  62. unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
  63. unsigned char rev[2]; /* 91 Revision Code */
  64. unsigned char mdate[2]; /* 93 Manufacturing Date */
  65. unsigned char sernum[4]; /* 95 Assembly Serial Number */
  66. unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */
  67. } ddr1_spd_eeprom_t;
  68. /*
  69. * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM",
  70. * SPD Revision 1.2
  71. */
  72. typedef struct ddr2_spd_eeprom_s {
  73. unsigned char info_size; /* 0 # bytes written into serial memory */
  74. unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
  75. unsigned char mem_type; /* 2 Fundamental memory type */
  76. unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
  77. unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
  78. unsigned char mod_ranks; /* 5 Number of DIMM Ranks */
  79. unsigned char dataw; /* 6 Module Data Width */
  80. unsigned char res_7; /* 7 Reserved */
  81. unsigned char voltage; /* 8 Voltage intf std of this assembly */
  82. unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */
  83. unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */
  84. unsigned char config; /* 11 DIMM Configuration type */
  85. unsigned char refresh; /* 12 Refresh Rate/Type */
  86. unsigned char primw; /* 13 Primary SDRAM Width */
  87. unsigned char ecw; /* 14 Error Checking SDRAM width */
  88. unsigned char res_15; /* 15 Reserved */
  89. unsigned char burstl; /* 16 Burst Lengths Supported */
  90. unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */
  91. unsigned char cas_lat; /* 18 CAS# Latencies Supported */
  92. unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */
  93. unsigned char dimm_type; /* 20 DIMM type information */
  94. unsigned char mod_attr; /* 21 SDRAM Module Attributes */
  95. unsigned char dev_attr; /* 22 SDRAM Device Attributes */
  96. unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */
  97. unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
  98. unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */
  99. unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
  100. unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
  101. unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
  102. unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
  103. unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
  104. unsigned char rank_dens; /* 31 Density of each rank on module */
  105. unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
  106. unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */
  107. unsigned char data_setup; /* 34 Data Input Setup Time
  108. Before Strobe (tDS) */
  109. unsigned char data_hold; /* 35 Data Input Hold Time
  110. After Strobe (tDH) */
  111. unsigned char twr; /* 36 Write Recovery time tWR */
  112. unsigned char twtr; /* 37 Int write to read delay tWTR */
  113. unsigned char trtp; /* 38 Int read to precharge delay tRTP */
  114. unsigned char mem_probe; /* 39 Mem analysis probe characteristics */
  115. unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
  116. unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
  117. unsigned char trfc; /* 42 Min Auto to Active period tRFC */
  118. unsigned char tckmax; /* 43 Max device cycle time tCKmax */
  119. unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
  120. unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */
  121. unsigned char pll_relock; /* 46 PLL Relock time */
  122. unsigned char t_casemax; /* 47 Tcasemax */
  123. unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from
  124. Top (Case) to Ambient (Psi T-A DRAM) */
  125. unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient
  126. due to Activate-Precharge/Mode Bits
  127. (DT0/Mode Bits) */
  128. unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient
  129. due to Precharge/Quiet Standby
  130. (DT2N/DT2Q) */
  131. unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient
  132. due to Precharge Power-Down (DT2P) */
  133. unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient
  134. due to Active Standby (DT3N) */
  135. unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient
  136. due to Active Power-Down with
  137. Fast PDN Exit (DT3Pfast) */
  138. unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient
  139. due to Active Power-Down with Slow
  140. PDN Exit (DT3Pslow) */
  141. unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
  142. due to Page Open Burst Read/DT4R4W
  143. Mode Bit (DT4R/DT4R4W Mode Bit) */
  144. unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient
  145. due to Burst Refresh (DT5B) */
  146. unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient
  147. due to Bank Interleave Reads with
  148. Auto-Precharge (DT7) */
  149. unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form
  150. Top (Case) to Ambient (Psi T-A PLL) */
  151. unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package
  152. from Top (Case) to Ambient
  153. (Psi T-A Register) */
  154. unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
  155. due to PLL Active (DT PLL Active) */
  156. unsigned char dtregact; /* 61 Register Case Temperature Rise from
  157. Ambient due to Register Active/Mode Bit
  158. (DT Register Active/Mode Bit) */
  159. unsigned char spd_rev; /* 62 SPD Data Revision Code */
  160. unsigned char cksum; /* 63 Checksum for bytes 0-62 */
  161. unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */
  162. unsigned char mloc; /* 72 Manufacturing Location */
  163. unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
  164. unsigned char rev[2]; /* 91 Revision Code */
  165. unsigned char mdate[2]; /* 93 Manufacturing Date */
  166. unsigned char sernum[4]; /* 95 Assembly Serial Number */
  167. unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */
  168. } ddr2_spd_eeprom_t;
  169. typedef struct ddr3_spd_eeprom_s {
  170. /* General Section: Bytes 0-59 */
  171. unsigned char info_size_crc; /* 0 # bytes written into serial memory,
  172. CRC coverage */
  173. unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */
  174. unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */
  175. unsigned char module_type; /* 3 Key Byte / Module Type */
  176. unsigned char density_banks; /* 4 SDRAM Density and Banks */
  177. unsigned char addressing; /* 5 SDRAM Addressing */
  178. unsigned char module_vdd; /* 6 Module nominal voltage, VDD */
  179. unsigned char organization; /* 7 Module Organization */
  180. unsigned char bus_width; /* 8 Module Memory Bus Width */
  181. unsigned char ftb_div; /* 9 Fine Timebase (FTB)
  182. Dividend / Divisor */
  183. unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */
  184. unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */
  185. unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */
  186. unsigned char res_13; /* 13 Reserved */
  187. unsigned char caslat_lsb; /* 14 CAS Latencies Supported,
  188. Least Significant Byte */
  189. unsigned char caslat_msb; /* 15 CAS Latencies Supported,
  190. Most Significant Byte */
  191. unsigned char taa_min; /* 16 Min CAS Latency Time */
  192. unsigned char twr_min; /* 17 Min Write REcovery Time */
  193. unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */
  194. unsigned char trrd_min; /* 19 Min Row Active to
  195. Row Active Delay Time */
  196. unsigned char trp_min; /* 20 Min Row Precharge Delay Time */
  197. unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */
  198. unsigned char tras_min_lsb; /* 22 Min Active to Precharge
  199. Delay Time */
  200. unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh
  201. Delay Time, LSB */
  202. unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */
  203. unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */
  204. unsigned char twtr_min; /* 26 Min Internal Write to
  205. Read Command Delay Time */
  206. unsigned char trtp_min; /* 27 Min Internal Read to Precharge
  207. Command Delay Time */
  208. unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */
  209. unsigned char tfaw_min; /* 29 Min Four Activate Window
  210. Delay Time*/
  211. unsigned char opt_features; /* 30 SDRAM Optional Features */
  212. unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
  213. unsigned char therm_sensor; /* 32 Module Thermal Sensor */
  214. unsigned char device_type; /* 33 SDRAM device type */
  215. int8_t fine_tck_min; /* 34 Fine offset for tCKmin */
  216. int8_t fine_taa_min; /* 35 Fine offset for tAAmin */
  217. int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */
  218. int8_t fine_trp_min; /* 37 Fine offset for tRPmin */
  219. int8_t fine_trc_min; /* 38 Fine offset for tRCmin */
  220. unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */
  221. /* Module-Specific Section: Bytes 60-116 */
  222. union {
  223. struct {
  224. /* 60 (Unbuffered) Module Nominal Height */
  225. unsigned char mod_height;
  226. /* 61 (Unbuffered) Module Maximum Thickness */
  227. unsigned char mod_thickness;
  228. /* 62 (Unbuffered) Reference Raw Card Used */
  229. unsigned char ref_raw_card;
  230. /* 63 (Unbuffered) Address Mapping from
  231. Edge Connector to DRAM */
  232. unsigned char addr_mapping;
  233. /* 64-116 (Unbuffered) Reserved */
  234. unsigned char res_64_116[53];
  235. } unbuffered;
  236. struct {
  237. /* 60 (Registered) Module Nominal Height */
  238. unsigned char mod_height;
  239. /* 61 (Registered) Module Maximum Thickness */
  240. unsigned char mod_thickness;
  241. /* 62 (Registered) Reference Raw Card Used */
  242. unsigned char ref_raw_card;
  243. /* 63 DIMM Module Attributes */
  244. unsigned char modu_attr;
  245. /* 64 RDIMM Thermal Heat Spreader Solution */
  246. unsigned char thermal;
  247. /* 65 Register Manufacturer ID Code, Least Significant Byte */
  248. unsigned char reg_id_lo;
  249. /* 66 Register Manufacturer ID Code, Most Significant Byte */
  250. unsigned char reg_id_hi;
  251. /* 67 Register Revision Number */
  252. unsigned char reg_rev;
  253. /* 68 Register Type */
  254. unsigned char reg_type;
  255. /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
  256. unsigned char rcw[8];
  257. } registered;
  258. unsigned char uc[57]; /* 60-116 Module-Specific Section */
  259. } mod_section;
  260. /* Unique Module ID: Bytes 117-125 */
  261. unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */
  262. unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */
  263. unsigned char mloc; /* 119 Mfg Location */
  264. unsigned char mdate[2]; /* 120-121 Mfg Date */
  265. unsigned char sernum[4]; /* 122-125 Module Serial Number */
  266. /* CRC: Bytes 126-127 */
  267. unsigned char crc[2]; /* 126-127 SPD CRC */
  268. /* Other Manufacturer Fields and User Space: Bytes 128-255 */
  269. unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */
  270. unsigned char mrev[2]; /* 146-147 Module Revision Code */
  271. unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */
  272. unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */
  273. unsigned char msd[26]; /* 150-175 Mfg's Specific Data */
  274. unsigned char cust[80]; /* 176-255 Open for Customer Use */
  275. } ddr3_spd_eeprom_t;
  276. /* From JEEC Standard No. 21-C release 23A */
  277. struct ddr4_spd_eeprom_s {
  278. /* General Section: Bytes 0-127 */
  279. uint8_t info_size_crc; /* 0 # bytes */
  280. uint8_t spd_rev; /* 1 Total # bytes of SPD */
  281. uint8_t mem_type; /* 2 Key Byte / mem type */
  282. uint8_t module_type; /* 3 Key Byte / Module Type */
  283. uint8_t density_banks; /* 4 Density and Banks */
  284. uint8_t addressing; /* 5 Addressing */
  285. uint8_t package_type; /* 6 Package type */
  286. uint8_t opt_feature; /* 7 Optional features */
  287. uint8_t thermal_ref; /* 8 Thermal and refresh */
  288. uint8_t oth_opt_features; /* 9 Other optional features */
  289. uint8_t res_10; /* 10 Reserved */
  290. uint8_t module_vdd; /* 11 Module nominal voltage */
  291. uint8_t organization; /* 12 Module Organization */
  292. uint8_t bus_width; /* 13 Module Memory Bus Width */
  293. uint8_t therm_sensor; /* 14 Module Thermal Sensor */
  294. uint8_t ext_type; /* 15 Extended module type */
  295. uint8_t res_16;
  296. uint8_t timebases; /* 17 MTb and FTB */
  297. uint8_t tck_min; /* 18 tCKAVGmin */
  298. uint8_t tck_max; /* 19 TCKAVGmax */
  299. uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
  300. uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
  301. uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
  302. uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
  303. uint8_t taa_min; /* 24 Min CAS Latency Time */
  304. uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
  305. uint8_t trp_min; /* 26 Min Row Precharge Delay Time */
  306. uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
  307. uint8_t tras_min_lsb; /* 28 tRASmin, lsb */
  308. uint8_t trc_min_lsb; /* 29 tRCmin, lsb */
  309. uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
  310. uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
  311. uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
  312. uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
  313. uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
  314. uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
  315. uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */
  316. uint8_t tfaw_min; /* 37 tFAW, lsb */
  317. uint8_t trrds_min; /* 38 tRRD_Smin, MTB */
  318. uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */
  319. uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */
  320. uint8_t res_41[60-41]; /* 41 Rserved */
  321. uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
  322. uint8_t res_78[117-78]; /* 78~116, Reserved */
  323. int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
  324. int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
  325. int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
  326. int8_t fine_trc_min; /* 120 Fine offset for tRCmin */
  327. int8_t fine_trp_min; /* 121 Fine offset for tRPmin */
  328. int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */
  329. int8_t fine_taa_min; /* 123 Fine offset for tAAmin */
  330. int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */
  331. int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */
  332. /* CRC: Bytes 126-127 */
  333. uint8_t crc[2]; /* 126-127 SPD CRC */
  334. /* Module-Specific Section: Bytes 128-255 */
  335. union {
  336. struct {
  337. /* 128 (Unbuffered) Module Nominal Height */
  338. uint8_t mod_height;
  339. /* 129 (Unbuffered) Module Maximum Thickness */
  340. uint8_t mod_thickness;
  341. /* 130 (Unbuffered) Reference Raw Card Used */
  342. uint8_t ref_raw_card;
  343. /* 131 (Unbuffered) Address Mapping from
  344. Edge Connector to DRAM */
  345. uint8_t addr_mapping;
  346. /* 132~253 (Unbuffered) Reserved */
  347. uint8_t res_132[254-132];
  348. /* 254~255 CRC */
  349. uint8_t crc[2];
  350. } unbuffered;
  351. struct {
  352. /* 128 (Registered) Module Nominal Height */
  353. uint8_t mod_height;
  354. /* 129 (Registered) Module Maximum Thickness */
  355. uint8_t mod_thickness;
  356. /* 130 (Registered) Reference Raw Card Used */
  357. uint8_t ref_raw_card;
  358. /* 131 DIMM Module Attributes */
  359. uint8_t modu_attr;
  360. /* 132 RDIMM Thermal Heat Spreader Solution */
  361. uint8_t thermal;
  362. /* 133 Register Manufacturer ID Code, LSB */
  363. uint8_t reg_id_lo;
  364. /* 134 Register Manufacturer ID Code, MSB */
  365. uint8_t reg_id_hi;
  366. /* 135 Register Revision Number */
  367. uint8_t reg_rev;
  368. /* 136 Address mapping from register to DRAM */
  369. u8 reg_map;
  370. u8 ca_stren;
  371. u8 clk_stren;
  372. /* 139~253 Reserved */
  373. u8 res_137[254 - 139];
  374. /* 254~255 CRC */
  375. uint8_t crc[2];
  376. } registered;
  377. struct {
  378. /* 128 (Loadreduced) Module Nominal Height */
  379. uint8_t mod_height;
  380. /* 129 (Loadreduced) Module Maximum Thickness */
  381. uint8_t mod_thickness;
  382. /* 130 (Loadreduced) Reference Raw Card Used */
  383. uint8_t ref_raw_card;
  384. /* 131 DIMM Module Attributes */
  385. uint8_t modu_attr;
  386. /* 132 RDIMM Thermal Heat Spreader Solution */
  387. uint8_t thermal;
  388. /* 133 Register Manufacturer ID Code, LSB */
  389. uint8_t reg_id_lo;
  390. /* 134 Register Manufacturer ID Code, MSB */
  391. uint8_t reg_id_hi;
  392. /* 135 Register Revision Number */
  393. uint8_t reg_rev;
  394. /* 136 Address mapping from register to DRAM */
  395. uint8_t reg_map;
  396. /* 137 Register Output Drive Strength for CMD/Add*/
  397. uint8_t reg_drv;
  398. /* 138 Register Output Drive Strength for CK */
  399. uint8_t reg_drv_ck;
  400. /* 139 Data Buffer Revision Number */
  401. uint8_t data_buf_rev;
  402. /* 140 DRAM VrefDQ for Package Rank 0 */
  403. uint8_t vrefqe_r0;
  404. /* 141 DRAM VrefDQ for Package Rank 1 */
  405. uint8_t vrefqe_r1;
  406. /* 142 DRAM VrefDQ for Package Rank 2 */
  407. uint8_t vrefqe_r2;
  408. /* 143 DRAM VrefDQ for Package Rank 3 */
  409. uint8_t vrefqe_r3;
  410. /* 144 Data Buffer VrefDQ for DRAM Interface */
  411. uint8_t data_intf;
  412. /*
  413. * 145 Data Buffer MDQ Drive Strength and RTT
  414. * for data rate <= 1866
  415. */
  416. uint8_t data_drv_1866;
  417. /*
  418. * 146 Data Buffer MDQ Drive Strength and RTT
  419. * for 1866 < data rate <= 2400
  420. */
  421. uint8_t data_drv_2400;
  422. /*
  423. * 147 Data Buffer MDQ Drive Strength and RTT
  424. * for 2400 < data rate <= 3200
  425. */
  426. uint8_t data_drv_3200;
  427. /* 148 DRAM Drive Strength */
  428. uint8_t dram_drv;
  429. /*
  430. * 149 DRAM ODT (RTT_WR, RTT_NOM)
  431. * for data rate <= 1866
  432. */
  433. uint8_t dram_odt_1866;
  434. /*
  435. * 150 DRAM ODT (RTT_WR, RTT_NOM)
  436. * for 1866 < data rate <= 2400
  437. */
  438. uint8_t dram_odt_2400;
  439. /*
  440. * 151 DRAM ODT (RTT_WR, RTT_NOM)
  441. * for 2400 < data rate <= 3200
  442. */
  443. uint8_t dram_odt_3200;
  444. /*
  445. * 152 DRAM ODT (RTT_PARK)
  446. * for data rate <= 1866
  447. */
  448. uint8_t dram_odt_park_1866;
  449. /*
  450. * 153 DRAM ODT (RTT_PARK)
  451. * for 1866 < data rate <= 2400
  452. */
  453. uint8_t dram_odt_park_2400;
  454. /*
  455. * 154 DRAM ODT (RTT_PARK)
  456. * for 2400 < data rate <= 3200
  457. */
  458. uint8_t dram_odt_park_3200;
  459. uint8_t res_155[254-155]; /* Reserved */
  460. /* 254~255 CRC */
  461. uint8_t crc[2];
  462. } loadreduced;
  463. uint8_t uc[128]; /* 128-255 Module-Specific Section */
  464. } mod_section;
  465. uint8_t res_256[320-256]; /* 256~319 Reserved */
  466. /* Module supplier's data: Byte 320~383 */
  467. uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */
  468. uint8_t mmid_msb; /* 321 Module MfgID Code MSB */
  469. uint8_t mloc; /* 322 Mfg Location */
  470. uint8_t mdate[2]; /* 323~324 Mfg Date */
  471. uint8_t sernum[4]; /* 325~328 Module Serial Number */
  472. uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */
  473. uint8_t mrev; /* 349 Module Revision Code */
  474. uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */
  475. uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */
  476. uint8_t stepping; /* 352 DRAM stepping */
  477. uint8_t msd[29]; /* 353~381 Mfg's Specific Data */
  478. uint8_t res_382[2]; /* 382~383 Reserved */
  479. uint8_t user[512-384]; /* 384~511 End User Programmable */
  480. };
  481. extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
  482. extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
  483. extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
  484. extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
  485. extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
  486. unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
  487. /*
  488. * Byte 2 Fundamental Memory Types.
  489. */
  490. #define SPD_MEMTYPE_FPM (0x01)
  491. #define SPD_MEMTYPE_EDO (0x02)
  492. #define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
  493. #define SPD_MEMTYPE_SDRAM (0x04)
  494. #define SPD_MEMTYPE_ROM (0x05)
  495. #define SPD_MEMTYPE_SGRAM (0x06)
  496. #define SPD_MEMTYPE_DDR (0x07)
  497. #define SPD_MEMTYPE_DDR2 (0x08)
  498. #define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
  499. #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A)
  500. #define SPD_MEMTYPE_DDR3 (0x0B)
  501. #define SPD_MEMTYPE_DDR4 (0x0C)
  502. /* DIMM Type for DDR2 SPD (according to v1.3) */
  503. #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00)
  504. #define DDR2_SPD_DIMMTYPE_RDIMM (0x01)
  505. #define DDR2_SPD_DIMMTYPE_UDIMM (0x02)
  506. #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04)
  507. #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06)
  508. #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07)
  509. #define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08)
  510. #define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10)
  511. #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20)
  512. /* Byte 3 Key Byte / Module Type for DDR3 SPD */
  513. #define DDR3_SPD_MODULETYPE_MASK (0x0f)
  514. #define DDR3_SPD_MODULETYPE_RDIMM (0x01)
  515. #define DDR3_SPD_MODULETYPE_UDIMM (0x02)
  516. #define DDR3_SPD_MODULETYPE_SO_DIMM (0x03)
  517. #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04)
  518. #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05)
  519. #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06)
  520. #define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07)
  521. #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
  522. #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
  523. #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A)
  524. #define DDR3_SPD_MODULETYPE_LRDIMM (0x0B)
  525. #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
  526. #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
  527. /* DIMM Type for DDR4 SPD */
  528. #define DDR4_SPD_MODULETYPE_MASK (0x0f)
  529. #define DDR4_SPD_MODULETYPE_EXT (0x00)
  530. #define DDR4_SPD_MODULETYPE_RDIMM (0x01)
  531. #define DDR4_SPD_MODULETYPE_UDIMM (0x02)
  532. #define DDR4_SPD_MODULETYPE_SO_DIMM (0x03)
  533. #define DDR4_SPD_MODULETYPE_LRDIMM (0x04)
  534. #define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05)
  535. #define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06)
  536. #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
  537. #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
  538. #define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
  539. #define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
  540. #endif /* _DDR_SPD_H_ */