xpedite550x.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010 Extreme Engineering Solutions, Inc.
  4. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  5. */
  6. /*
  7. * xpedite550x board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_SYS_BOARD_NAME "XPedite5500"
  15. #define CONFIG_SYS_FORM_PMC_XMC 1
  16. #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
  17. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  18. #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
  19. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  20. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  21. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  22. /*
  23. * Multicore config
  24. */
  25. #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
  26. #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
  27. /*
  28. * DDR config
  29. */
  30. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  31. #define CONFIG_DDR_SPD
  32. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  33. #define SPD_EEPROM_ADDRESS 0x54
  34. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  35. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  36. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  37. #define CONFIG_DDR_ECC
  38. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  39. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  40. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  41. #define CONFIG_VERY_BIG_RAM
  42. #ifndef __ASSEMBLY__
  43. extern unsigned long get_board_sys_clk(unsigned long dummy);
  44. extern unsigned long get_board_ddr_clk(unsigned long dummy);
  45. #endif
  46. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  47. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  48. /*
  49. * These can be toggled for performance analysis, otherwise use default.
  50. */
  51. #define CONFIG_L2_CACHE /* toggle L2 cache */
  52. #define CONFIG_BTB /* toggle branch predition */
  53. #define CONFIG_ENABLE_36BIT_PHYS 1
  54. #define CONFIG_SYS_CCSRBAR 0xef000000
  55. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  56. /*
  57. * Diagnostics
  58. */
  59. #define CONFIG_SYS_MEMTEST_START 0x10000000
  60. #define CONFIG_SYS_MEMTEST_END 0x20000000
  61. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  62. CONFIG_SYS_POST_I2C)
  63. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
  64. CONFIG_SYS_I2C_LM75_ADDR, \
  65. CONFIG_SYS_I2C_LM90_ADDR, \
  66. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  67. CONFIG_SYS_I2C_PCA953X_ADDR2, \
  68. CONFIG_SYS_I2C_PCA953X_ADDR3, \
  69. CONFIG_SYS_I2C_RTC_ADDR}
  70. /*
  71. * Memory map
  72. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  73. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  74. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  75. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  76. * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
  77. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  78. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  79. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  80. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  81. */
  82. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  83. /*
  84. * NAND flash configuration
  85. */
  86. #define CONFIG_SYS_NAND_BASE 0xef800000
  87. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  88. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
  89. CONFIG_SYS_NAND_BASE2}
  90. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  91. #define CONFIG_NAND_FSL_ELBC
  92. /*
  93. * NOR flash configuration
  94. */
  95. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  96. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  97. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  98. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  99. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  100. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  101. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  102. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  103. {0xf7f40000, 0xc0000} }
  104. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  105. /*
  106. * Chip select configuration
  107. */
  108. /* NOR Flash 0 on CS0 */
  109. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  110. BR_PS_16 | \
  111. BR_V)
  112. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
  113. OR_GPCM_CSNT | \
  114. OR_GPCM_XACS | \
  115. OR_GPCM_ACS_DIV2 | \
  116. OR_GPCM_SCY_8 | \
  117. OR_GPCM_TRLX | \
  118. OR_GPCM_EHTR | \
  119. OR_GPCM_EAD)
  120. /* NOR Flash 1 on CS1 */
  121. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  122. BR_PS_16 | \
  123. BR_V)
  124. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  125. /* NAND flash on CS2 */
  126. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  127. (2<<BR_DECC_SHIFT) | \
  128. BR_PS_8 | \
  129. BR_MS_FCM | \
  130. BR_V)
  131. /* NAND flash on CS2 */
  132. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  133. OR_FCM_PGS | \
  134. OR_FCM_CSCT | \
  135. OR_FCM_CST | \
  136. OR_FCM_CHT | \
  137. OR_FCM_SCY_1 | \
  138. OR_FCM_TRLX | \
  139. OR_FCM_EHTR)
  140. /* NAND flash on CS3 */
  141. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  142. (2<<BR_DECC_SHIFT) | \
  143. BR_PS_8 | \
  144. BR_MS_FCM | \
  145. BR_V)
  146. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  147. /*
  148. * Use L1 as initial stack
  149. */
  150. #define CONFIG_SYS_INIT_RAM_LOCK 1
  151. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  152. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  153. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  154. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  155. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  156. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  157. /*
  158. * Serial Port
  159. */
  160. #define CONFIG_SYS_NS16550_SERIAL
  161. #define CONFIG_SYS_NS16550_REG_SIZE 1
  162. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  163. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  164. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  165. #define CONFIG_SYS_BAUDRATE_TABLE \
  166. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  167. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  168. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  169. /*
  170. * I2C
  171. */
  172. #define CONFIG_SYS_I2C
  173. #define CONFIG_SYS_I2C_FSL
  174. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  175. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  176. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  177. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  178. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  179. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  180. /* I2C DS7505 temperature sensor */
  181. #define CONFIG_SYS_I2C_LM75_ADDR 0x48
  182. /* I2C ADT7461 temperature sensor */
  183. #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
  184. /* I2C EEPROM - AT24C128B */
  185. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  186. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  187. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  188. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  189. /* I2C RTC */
  190. #define CONFIG_RTC_M41T11 1
  191. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  192. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  193. /* GPIO */
  194. #define CONFIG_PCA953X
  195. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  196. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  197. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  198. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  199. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  200. /*
  201. * GPIO pin definitions, PU = pulled high, PD = pulled low
  202. */
  203. /* PCA9557 @ 0x18*/
  204. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  205. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
  206. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  207. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
  208. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  209. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
  210. /* PCA9557 @ 0x1e*/
  211. #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
  212. #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
  213. #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
  214. #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
  215. #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
  216. #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
  217. #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
  218. /* PCA9557 @ 0x1f */
  219. #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
  220. #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
  221. #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
  222. #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
  223. #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
  224. #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
  225. #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
  226. #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
  227. /*
  228. * General PCI
  229. * Memory space is mapped 1-1, but I/O space must start from 0.
  230. */
  231. /* controller 1 - PEX8112 or XMC, depending on build option */
  232. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  233. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  234. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  235. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  236. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  237. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  238. /*
  239. * Networking options
  240. */
  241. #define CONFIG_TSEC_TBI
  242. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  243. #define CONFIG_ETHPRIME "eTSEC2"
  244. /*
  245. * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
  246. * 1000mbps SGMII link
  247. */
  248. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  249. TBICR_PHY_RESET \
  250. | TBICR_FULL_DUPLEX \
  251. | TBICR_SPEED1_SET \
  252. )
  253. #define CONFIG_TSEC1 1
  254. #define CONFIG_TSEC1_NAME "eTSEC1"
  255. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  256. #define TSEC1_PHY_ADDR 1
  257. #define TSEC1_PHYIDX 0
  258. #define CONFIG_HAS_ETH0
  259. #define CONFIG_TSEC2 1
  260. #define CONFIG_TSEC2_NAME "eTSEC2"
  261. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  262. #define TSEC2_PHY_ADDR 2
  263. #define TSEC2_PHYIDX 0
  264. #define CONFIG_HAS_ETH1
  265. #define CONFIG_TSEC3 1
  266. #define CONFIG_TSEC3_NAME "eTSEC3"
  267. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  268. #define TSEC3_PHY_ADDR 3
  269. #define TSEC3_PHYIDX 0
  270. #define CONFIG_HAS_ETH2
  271. /*
  272. * USB
  273. */
  274. #define CONFIG_USB_EHCI_FSL
  275. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  276. /*
  277. * Miscellaneous configurable options
  278. */
  279. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  280. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  281. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  282. /*
  283. * For booting Linux, the board info and command line data
  284. * have to be in the first 16 MB of memory, since this is
  285. * the maximum mapped by the Linux kernel during initialization.
  286. */
  287. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  288. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  289. /*
  290. * Environment Configuration
  291. */
  292. /*
  293. * Flash memory map:
  294. * fff80000 - ffffffff Pri U-Boot (512 KB)
  295. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  296. * fff00000 - fff3ffff Pri FDT (256KB)
  297. * fef00000 - ffefffff Pri OS image (16MB)
  298. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  299. *
  300. * f7f80000 - f7ffffff Sec U-Boot (512 KB)
  301. * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
  302. * f7f00000 - f7f3ffff Sec FDT (256KB)
  303. * f6f00000 - f7efffff Sec OS image (16MB)
  304. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  305. */
  306. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  307. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
  308. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  309. #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
  310. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  311. #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
  312. #define CONFIG_PROG_UBOOT1 \
  313. "$download_cmd $loadaddr $ubootfile; " \
  314. "if test $? -eq 0; then " \
  315. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  316. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  317. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  318. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  319. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  320. "if test $? -ne 0; then " \
  321. "echo PROGRAM FAILED; " \
  322. "else; " \
  323. "echo PROGRAM SUCCEEDED; " \
  324. "fi; " \
  325. "else; " \
  326. "echo DOWNLOAD FAILED; " \
  327. "fi;"
  328. #define CONFIG_PROG_UBOOT2 \
  329. "$download_cmd $loadaddr $ubootfile; " \
  330. "if test $? -eq 0; then " \
  331. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  332. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  333. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  334. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  335. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  336. "if test $? -ne 0; then " \
  337. "echo PROGRAM FAILED; " \
  338. "else; " \
  339. "echo PROGRAM SUCCEEDED; " \
  340. "fi; " \
  341. "else; " \
  342. "echo DOWNLOAD FAILED; " \
  343. "fi;"
  344. #define CONFIG_BOOT_OS_NET \
  345. "$download_cmd $osaddr $osfile; " \
  346. "if test $? -eq 0; then " \
  347. "if test -n $fdtaddr; then " \
  348. "$download_cmd $fdtaddr $fdtfile; " \
  349. "if test $? -eq 0; then " \
  350. "bootm $osaddr - $fdtaddr; " \
  351. "else; " \
  352. "echo FDT DOWNLOAD FAILED; " \
  353. "fi; " \
  354. "else; " \
  355. "bootm $osaddr; " \
  356. "fi; " \
  357. "else; " \
  358. "echo OS DOWNLOAD FAILED; " \
  359. "fi;"
  360. #define CONFIG_PROG_OS1 \
  361. "$download_cmd $osaddr $osfile; " \
  362. "if test $? -eq 0; then " \
  363. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  364. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  365. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  366. "if test $? -ne 0; then " \
  367. "echo OS PROGRAM FAILED; " \
  368. "else; " \
  369. "echo OS PROGRAM SUCCEEDED; " \
  370. "fi; " \
  371. "else; " \
  372. "echo OS DOWNLOAD FAILED; " \
  373. "fi;"
  374. #define CONFIG_PROG_OS2 \
  375. "$download_cmd $osaddr $osfile; " \
  376. "if test $? -eq 0; then " \
  377. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  378. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  379. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  380. "if test $? -ne 0; then " \
  381. "echo OS PROGRAM FAILED; " \
  382. "else; " \
  383. "echo OS PROGRAM SUCCEEDED; " \
  384. "fi; " \
  385. "else; " \
  386. "echo OS DOWNLOAD FAILED; " \
  387. "fi;"
  388. #define CONFIG_PROG_FDT1 \
  389. "$download_cmd $fdtaddr $fdtfile; " \
  390. "if test $? -eq 0; then " \
  391. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  392. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  393. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  394. "if test $? -ne 0; then " \
  395. "echo FDT PROGRAM FAILED; " \
  396. "else; " \
  397. "echo FDT PROGRAM SUCCEEDED; " \
  398. "fi; " \
  399. "else; " \
  400. "echo FDT DOWNLOAD FAILED; " \
  401. "fi;"
  402. #define CONFIG_PROG_FDT2 \
  403. "$download_cmd $fdtaddr $fdtfile; " \
  404. "if test $? -eq 0; then " \
  405. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  406. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  407. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  408. "if test $? -ne 0; then " \
  409. "echo FDT PROGRAM FAILED; " \
  410. "else; " \
  411. "echo FDT PROGRAM SUCCEEDED; " \
  412. "fi; " \
  413. "else; " \
  414. "echo FDT DOWNLOAD FAILED; " \
  415. "fi;"
  416. #define CONFIG_EXTRA_ENV_SETTINGS \
  417. "autoload=yes\0" \
  418. "download_cmd=tftp\0" \
  419. "console_args=console=ttyS0,115200\0" \
  420. "root_args=root=/dev/nfs rw\0" \
  421. "misc_args=ip=on\0" \
  422. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  423. "bootfile=/home/user/file\0" \
  424. "osfile=/home/user/board.uImage\0" \
  425. "fdtfile=/home/user/board.dtb\0" \
  426. "ubootfile=/home/user/u-boot.bin\0" \
  427. "fdtaddr=0x1e00000\0" \
  428. "osaddr=0x1000000\0" \
  429. "loadaddr=0x1000000\0" \
  430. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  431. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  432. "prog_os1="CONFIG_PROG_OS1"\0" \
  433. "prog_os2="CONFIG_PROG_OS2"\0" \
  434. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  435. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  436. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  437. "bootcmd_flash1=run set_bootargs; " \
  438. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  439. "bootcmd_flash2=run set_bootargs; " \
  440. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  441. "bootcmd=run bootcmd_flash1\0"
  442. #endif /* __CONFIG_H */