xpedite520x.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008 Extreme Engineering Solutions, Inc.
  4. * Copyright 2004-2008 Freescale Semiconductor, Inc.
  5. */
  6. /*
  7. * xpedite520x board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_SYS_BOARD_NAME "XPedite5200"
  15. #define CONFIG_SYS_FORM_PMC_XMC 1
  16. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  17. #define CONFIG_PCI1 1 /* PCI controller 1 */
  18. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  19. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  20. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  21. /*
  22. * DDR config
  23. */
  24. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  25. #define CONFIG_DDR_SPD
  26. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  27. #define SPD_EEPROM_ADDRESS 0x54
  28. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  29. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  30. #define CONFIG_DDR_ECC
  31. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  32. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  33. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  34. #define CONFIG_VERY_BIG_RAM
  35. #define CONFIG_SYS_CLK_FREQ 66666666
  36. /*
  37. * These can be toggled for performance analysis, otherwise use default.
  38. */
  39. #define CONFIG_L2_CACHE /* toggle L2 cache */
  40. #define CONFIG_BTB /* toggle branch predition */
  41. #define CONFIG_ENABLE_36BIT_PHYS 1
  42. #define CONFIG_SYS_CCSRBAR 0xef000000
  43. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  44. /*
  45. * Diagnostics
  46. */
  47. #define CONFIG_SYS_MEMTEST_START 0x10000000
  48. #define CONFIG_SYS_MEMTEST_END 0x20000000
  49. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  50. CONFIG_SYS_POST_I2C)
  51. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
  52. CONFIG_SYS_I2C_EEPROM_ADDR, \
  53. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  54. CONFIG_SYS_I2C_PCA953X_ADDR1, \
  55. CONFIG_SYS_I2C_RTC_ADDR}
  56. /*
  57. * Memory map
  58. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  59. * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
  60. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  61. * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
  62. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  63. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  64. * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
  65. * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
  66. */
  67. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  68. /*
  69. * NAND flash configuration
  70. */
  71. #define CONFIG_SYS_NAND_BASE 0xef800000
  72. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  73. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  74. #define CONFIG_NAND_ACTL
  75. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
  76. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
  77. #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
  78. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  79. /*
  80. * NOR flash configuration
  81. */
  82. #define CONFIG_SYS_FLASH_BASE 0xfc000000
  83. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  84. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  85. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  86. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  87. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  88. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  89. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  90. {0xfbf40000, 0xc0000} }
  91. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  92. /*
  93. * Chip select configuration
  94. */
  95. /* NOR Flash 0 on CS0 */
  96. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  97. BR_PS_16 | \
  98. BR_V)
  99. #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
  100. OR_GPCM_ACS_DIV4 | \
  101. OR_GPCM_SCY_8)
  102. /* NOR Flash 1 on CS1 */
  103. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  104. BR_PS_16 | \
  105. BR_V)
  106. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  107. /* NAND flash on CS2 */
  108. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  109. BR_PS_8 | \
  110. BR_V)
  111. /* NAND flash on CS2 */
  112. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  113. OR_GPCM_BCTLD | \
  114. OR_GPCM_CSNT | \
  115. OR_GPCM_ACS_DIV4 | \
  116. OR_GPCM_SCY_4 | \
  117. OR_GPCM_TRLX | \
  118. OR_GPCM_EHTR)
  119. /* NAND flash on CS3 */
  120. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  121. BR_PS_8 | \
  122. BR_V)
  123. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  124. /*
  125. * Use L1 as initial stack
  126. */
  127. #define CONFIG_SYS_INIT_RAM_LOCK 1
  128. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  129. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
  130. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  131. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  132. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  133. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  134. /*
  135. * Serial Port
  136. */
  137. #define CONFIG_SYS_NS16550_SERIAL
  138. #define CONFIG_SYS_NS16550_REG_SIZE 1
  139. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  140. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  141. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  142. #define CONFIG_SYS_BAUDRATE_TABLE \
  143. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  144. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  145. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  146. /*
  147. * I2C
  148. */
  149. #define CONFIG_SYS_I2C
  150. #define CONFIG_SYS_I2C_FSL
  151. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  152. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  153. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  154. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  155. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  156. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  157. /* I2C EEPROM */
  158. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  159. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  160. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  161. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  162. /* I2C RTC */
  163. #define CONFIG_RTC_M41T11 1
  164. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  165. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  166. /* GPIO */
  167. #define CONFIG_PCA953X
  168. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  169. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
  170. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  171. /* PCA957 @ 0x18 */
  172. #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
  173. #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
  174. #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
  175. #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
  176. #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
  177. #define CONFIG_SYS_PCA953X_NVM_WP 0x20
  178. #define CONFIG_SYS_PCA953X_MONARCH 0x40
  179. #define CONFIG_SYS_PCA953X_EREADY 0x80
  180. /* PCA957 @ 0x19 */
  181. #define CONFIG_SYS_PCA953X_P14_IO0 0x01
  182. #define CONFIG_SYS_PCA953X_P14_IO1 0x02
  183. #define CONFIG_SYS_PCA953X_P14_IO2 0x04
  184. #define CONFIG_SYS_PCA953X_P14_IO3 0x08
  185. #define CONFIG_SYS_PCA953X_P14_IO4 0x10
  186. #define CONFIG_SYS_PCA953X_P14_IO5 0x20
  187. #define CONFIG_SYS_PCA953X_P14_IO6 0x40
  188. #define CONFIG_SYS_PCA953X_P14_IO7 0x80
  189. /* 12-bit ADC used to measure CPU diode */
  190. #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
  191. /*
  192. * General PCI
  193. * Memory space is mapped 1-1, but I/O space must start from 0.
  194. */
  195. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  196. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  197. #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
  198. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  199. #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
  200. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
  201. /*
  202. * Networking options
  203. */
  204. #define CONFIG_ETHPRIME "eTSEC1"
  205. #define CONFIG_TSEC1 1
  206. #define CONFIG_TSEC1_NAME "eTSEC1"
  207. #define TSEC1_FLAGS TSEC_GIGABIT
  208. #define TSEC1_PHY_ADDR 1
  209. #define TSEC1_PHYIDX 0
  210. #define CONFIG_HAS_ETH0
  211. #define CONFIG_TSEC2 1
  212. #define CONFIG_TSEC2_NAME "eTSEC2"
  213. #define TSEC2_FLAGS TSEC_GIGABIT
  214. #define TSEC2_PHY_ADDR 2
  215. #define TSEC2_PHYIDX 0
  216. #define CONFIG_HAS_ETH1
  217. #define CONFIG_TSEC3 1
  218. #define CONFIG_TSEC3_NAME "eTSEC3"
  219. #define TSEC3_FLAGS TSEC_GIGABIT
  220. #define TSEC3_PHY_ADDR 3
  221. #define TSEC3_PHYIDX 0
  222. #define CONFIG_HAS_ETH2
  223. #define CONFIG_TSEC4 1
  224. #define CONFIG_TSEC4_NAME "eTSEC4"
  225. #define TSEC4_FLAGS TSEC_GIGABIT
  226. #define TSEC4_PHY_ADDR 4
  227. #define TSEC4_PHYIDX 0
  228. #define CONFIG_HAS_ETH3
  229. /*
  230. * BOOTP options
  231. */
  232. #define CONFIG_BOOTP_BOOTFILESIZE
  233. /*
  234. * Miscellaneous configurable options
  235. */
  236. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  237. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  238. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  239. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  240. /*
  241. * For booting Linux, the board info and command line data
  242. * have to be in the first 16 MB of memory, since this is
  243. * the maximum mapped by the Linux kernel during initialization.
  244. */
  245. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  246. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  247. /*
  248. * Environment Configuration
  249. */
  250. /*
  251. * Flash memory map:
  252. * fff80000 - ffffffff Pri U-Boot (512 KB)
  253. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  254. * fff00000 - fff3ffff Pri FDT (256KB)
  255. * fef00000 - ffefffff Pri OS image (16MB)
  256. * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
  257. *
  258. * fbf80000 - fbffffff Sec U-Boot (512 KB)
  259. * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
  260. * fbf00000 - fbf3ffff Sec FDT (256KB)
  261. * faf00000 - fbefffff Sec OS image (16MB)
  262. * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
  263. */
  264. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  265. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
  266. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  267. #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
  268. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  269. #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
  270. #define CONFIG_PROG_UBOOT1 \
  271. "$download_cmd $loadaddr $ubootfile; " \
  272. "if test $? -eq 0; then " \
  273. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  274. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  275. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  276. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  277. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  278. "if test $? -ne 0; then " \
  279. "echo PROGRAM FAILED; " \
  280. "else; " \
  281. "echo PROGRAM SUCCEEDED; " \
  282. "fi; " \
  283. "else; " \
  284. "echo DOWNLOAD FAILED; " \
  285. "fi;"
  286. #define CONFIG_PROG_UBOOT2 \
  287. "$download_cmd $loadaddr $ubootfile; " \
  288. "if test $? -eq 0; then " \
  289. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  290. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  291. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  292. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  293. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  294. "if test $? -ne 0; then " \
  295. "echo PROGRAM FAILED; " \
  296. "else; " \
  297. "echo PROGRAM SUCCEEDED; " \
  298. "fi; " \
  299. "else; " \
  300. "echo DOWNLOAD FAILED; " \
  301. "fi;"
  302. #define CONFIG_BOOT_OS_NET \
  303. "$download_cmd $osaddr $osfile; " \
  304. "if test $? -eq 0; then " \
  305. "if test -n $fdtaddr; then " \
  306. "$download_cmd $fdtaddr $fdtfile; " \
  307. "if test $? -eq 0; then " \
  308. "bootm $osaddr - $fdtaddr; " \
  309. "else; " \
  310. "echo FDT DOWNLOAD FAILED; " \
  311. "fi; " \
  312. "else; " \
  313. "bootm $osaddr; " \
  314. "fi; " \
  315. "else; " \
  316. "echo OS DOWNLOAD FAILED; " \
  317. "fi;"
  318. #define CONFIG_PROG_OS1 \
  319. "$download_cmd $osaddr $osfile; " \
  320. "if test $? -eq 0; then " \
  321. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  322. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  323. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  324. "if test $? -ne 0; then " \
  325. "echo OS PROGRAM FAILED; " \
  326. "else; " \
  327. "echo OS PROGRAM SUCCEEDED; " \
  328. "fi; " \
  329. "else; " \
  330. "echo OS DOWNLOAD FAILED; " \
  331. "fi;"
  332. #define CONFIG_PROG_OS2 \
  333. "$download_cmd $osaddr $osfile; " \
  334. "if test $? -eq 0; then " \
  335. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  336. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  337. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  338. "if test $? -ne 0; then " \
  339. "echo OS PROGRAM FAILED; " \
  340. "else; " \
  341. "echo OS PROGRAM SUCCEEDED; " \
  342. "fi; " \
  343. "else; " \
  344. "echo OS DOWNLOAD FAILED; " \
  345. "fi;"
  346. #define CONFIG_PROG_FDT1 \
  347. "$download_cmd $fdtaddr $fdtfile; " \
  348. "if test $? -eq 0; then " \
  349. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  350. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  351. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  352. "if test $? -ne 0; then " \
  353. "echo FDT PROGRAM FAILED; " \
  354. "else; " \
  355. "echo FDT PROGRAM SUCCEEDED; " \
  356. "fi; " \
  357. "else; " \
  358. "echo FDT DOWNLOAD FAILED; " \
  359. "fi;"
  360. #define CONFIG_PROG_FDT2 \
  361. "$download_cmd $fdtaddr $fdtfile; " \
  362. "if test $? -eq 0; then " \
  363. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  364. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  365. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  366. "if test $? -ne 0; then " \
  367. "echo FDT PROGRAM FAILED; " \
  368. "else; " \
  369. "echo FDT PROGRAM SUCCEEDED; " \
  370. "fi; " \
  371. "else; " \
  372. "echo FDT DOWNLOAD FAILED; " \
  373. "fi;"
  374. #define CONFIG_EXTRA_ENV_SETTINGS \
  375. "autoload=yes\0" \
  376. "download_cmd=tftp\0" \
  377. "console_args=console=ttyS0,115200\0" \
  378. "root_args=root=/dev/nfs rw\0" \
  379. "misc_args=ip=on\0" \
  380. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  381. "bootfile=/home/user/file\0" \
  382. "osfile=/home/user/board.uImage\0" \
  383. "fdtfile=/home/user/board.dtb\0" \
  384. "ubootfile=/home/user/u-boot.bin\0" \
  385. "fdtaddr=0x1e00000\0" \
  386. "osaddr=0x1000000\0" \
  387. "loadaddr=0x1000000\0" \
  388. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  389. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  390. "prog_os1="CONFIG_PROG_OS1"\0" \
  391. "prog_os2="CONFIG_PROG_OS2"\0" \
  392. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  393. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  394. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  395. "bootcmd_flash1=run set_bootargs; " \
  396. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  397. "bootcmd_flash2=run set_bootargs; " \
  398. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  399. "bootcmd=run bootcmd_flash1\0"
  400. #endif /* __CONFIG_H */