work_92105.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * WORK Microwave work_92105 board configuration file
  4. *
  5. * (C) Copyright 2014 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  7. */
  8. #ifndef __CONFIG_WORK_92105_H__
  9. #define __CONFIG_WORK_92105_H__
  10. /* SoC and board defines */
  11. #include <linux/sizes.h>
  12. #include <asm/arch/cpu.h>
  13. /*
  14. * Define work_92105 machine type by hand -- done only for compatibility
  15. * with original board code
  16. */
  17. #define CONFIG_MACH_TYPE 736
  18. #if !defined(CONFIG_SPL_BUILD)
  19. #define CONFIG_SKIP_LOWLEVEL_INIT
  20. #endif
  21. /*
  22. * Memory configurations
  23. */
  24. #define CONFIG_SYS_MALLOC_LEN SZ_1M
  25. #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
  26. #define CONFIG_SYS_SDRAM_SIZE SZ_128M
  27. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  28. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
  29. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  30. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
  31. - GENERATED_GBL_DATA_SIZE)
  32. /*
  33. * Serial Driver
  34. */
  35. #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
  36. /*
  37. * Ethernet Driver
  38. */
  39. #define CONFIG_PHY_SMSC
  40. #define CONFIG_LPC32XX_ETH
  41. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  42. /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
  43. /*
  44. * I2C driver
  45. */
  46. #define CONFIG_SYS_I2C_LPC32XX
  47. #define CONFIG_SYS_I2C
  48. #define CONFIG_SYS_I2C_SPEED 350000
  49. /*
  50. * I2C EEPROM
  51. */
  52. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
  53. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  54. /*
  55. * I2C RTC
  56. */
  57. #define CONFIG_RTC_DS1374
  58. /*
  59. * U-Boot General Configurations
  60. */
  61. #define CONFIG_SYS_CBSIZE 1024
  62. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  63. /*
  64. * NAND chip timings for FIXME: which one?
  65. */
  66. #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
  67. #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
  68. #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
  69. #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
  70. #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
  71. #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
  72. #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
  73. /*
  74. * NAND
  75. */
  76. /* driver configuration */
  77. #define CONFIG_SYS_NAND_SELF_INIT
  78. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  79. #define CONFIG_SYS_MAX_NAND_CHIPS 1
  80. #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
  81. #define CONFIG_NAND_LPC32XX_MLC
  82. /*
  83. * GPIO
  84. */
  85. #define CONFIG_LPC32XX_GPIO
  86. /*
  87. * SSP/SPI/DISPLAY
  88. */
  89. #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
  90. /*
  91. * Environment
  92. */
  93. /*
  94. * Boot Linux
  95. */
  96. #define CONFIG_CMDLINE_TAG
  97. #define CONFIG_SETUP_MEMORY_TAGS
  98. #define CONFIG_INITRD_TAG
  99. #define CONFIG_BOOTFILE "uImage"
  100. #define CONFIG_LOADADDR 0x80008000
  101. /*
  102. * SPL
  103. */
  104. /* SPL will be executed at offset 0 */
  105. /* SPL will use SRAM as stack */
  106. #define CONFIG_SPL_STACK 0x0000FFF8
  107. /* Use the framework and generic lib */
  108. /* SPL will use serial */
  109. /* SPL will load U-Boot from NAND offset 0x40000 */
  110. #define CONFIG_SPL_NAND_DRIVERS
  111. #define CONFIG_SPL_NAND_BASE
  112. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
  113. #define CONFIG_SPL_PAD_TO 0x20000
  114. /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
  115. #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
  116. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  117. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  118. /*
  119. * Include SoC specific configuration
  120. */
  121. #include <asm/arch/config.h>
  122. #endif /* __CONFIG_WORK_92105_H__*/