vme8349.h 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * esd vme8349 U-Boot configuration file
  4. * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
  5. *
  6. * (C) Copyright 2006-2010
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * reinhard.arlt@esd-electronics.de
  10. * Based on the MPC8349EMDS config.
  11. */
  12. /*
  13. * vme8349 board configuration file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. /*
  18. * High Level Configuration Options
  19. */
  20. #define CONFIG_E300 1 /* E300 Family */
  21. /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  22. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  23. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  24. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  25. #define CONFIG_SYS_MEMTEST_END 0x00100000
  26. /*
  27. * DDR Setup
  28. */
  29. #define CONFIG_DDR_ECC /* only for ECC DDR module */
  30. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  31. #define CONFIG_SPD_EEPROM
  32. #define SPD_EEPROM_ADDRESS 0x54
  33. #define CONFIG_SYS_READ_SPD vme8349_read_spd
  34. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
  35. /*
  36. * 32-bit data path mode.
  37. *
  38. * Please note that using this mode for devices with the real density of 64-bit
  39. * effectively reduces the amount of available memory due to the effect of
  40. * wrapping around while translating address to row/columns, for example in the
  41. * 256MB module the upper 128MB get aliased with contents of the lower
  42. * 128MB); normally this define should be used for devices with real 32-bit
  43. * data path.
  44. */
  45. #undef CONFIG_DDR_32BIT
  46. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
  47. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  48. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  49. #define CONFIG_DDR_2T_TIMING
  50. #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
  51. | DDRCDR_ODT \
  52. | DDRCDR_Q_DRN)
  53. /* 0x80080001 */
  54. /*
  55. * FLASH on the Local Bus
  56. */
  57. #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
  58. #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
  59. #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
  60. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  61. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
  62. #undef CONFIG_SYS_FLASH_CHECKSUM
  63. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
  64. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
  65. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  66. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  67. #define CONFIG_SYS_RAMBOOT
  68. #else
  69. #undef CONFIG_SYS_RAMBOOT
  70. #endif
  71. #define CONFIG_SYS_INIT_RAM_LOCK 1
  72. #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
  73. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
  74. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  75. GENERATED_GBL_DATA_SIZE)
  76. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  77. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
  78. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
  79. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  80. /*
  81. * Serial Port
  82. */
  83. #define CONFIG_SYS_NS16550_SERIAL
  84. #define CONFIG_SYS_NS16550_REG_SIZE 1
  85. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  86. #define CONFIG_SYS_BAUDRATE_TABLE \
  87. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  88. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  89. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  90. /* I2C */
  91. #define CONFIG_SYS_I2C
  92. #define CONFIG_SYS_I2C_FSL
  93. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  94. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  95. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  96. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  97. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  98. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  99. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  100. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  101. #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
  102. /* TSEC */
  103. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  104. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  105. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  106. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
  107. /*
  108. * General PCI
  109. * Addresses are mapped 1-1.
  110. */
  111. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  112. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  113. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  114. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  115. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  116. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  117. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  118. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  119. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  120. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  121. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  122. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  123. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  124. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  125. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  126. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  127. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  128. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  129. #if defined(CONFIG_PCI)
  130. #undef CONFIG_EEPRO100
  131. #undef CONFIG_TULIP
  132. #if !defined(CONFIG_PCI_PNP)
  133. #define PCI_ENET0_IOADDR 0xFIXME
  134. #define PCI_ENET0_MEMADDR 0xFIXME
  135. #define PCI_IDSEL_NUMBER 0xFIXME
  136. #endif
  137. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  138. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  139. #endif /* CONFIG_PCI */
  140. /*
  141. * TSEC configuration
  142. */
  143. #if defined(CONFIG_TSEC_ENET)
  144. #define CONFIG_GMII /* MII PHY management */
  145. #define CONFIG_TSEC1
  146. #define CONFIG_TSEC1_NAME "TSEC0"
  147. #define CONFIG_TSEC2
  148. #define CONFIG_TSEC2_NAME "TSEC1"
  149. #define CONFIG_PHY_M88E1111
  150. #define TSEC1_PHY_ADDR 0x08
  151. #define TSEC2_PHY_ADDR 0x10
  152. #define TSEC1_PHYIDX 0
  153. #define TSEC2_PHYIDX 0
  154. #define TSEC1_FLAGS TSEC_GIGABIT
  155. #define TSEC2_FLAGS TSEC_GIGABIT
  156. /* Options are: TSEC[0-1] */
  157. #define CONFIG_ETHPRIME "TSEC0"
  158. #endif /* CONFIG_TSEC_ENET */
  159. /*
  160. * Environment
  161. */
  162. #ifndef CONFIG_SYS_RAMBOOT
  163. /* Address and size of Redundant Environment Sector */
  164. #endif
  165. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  166. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  167. /*
  168. * BOOTP options
  169. */
  170. #define CONFIG_BOOTP_BOOTFILESIZE
  171. /*
  172. * Command line configuration.
  173. */
  174. #define CONFIG_SYS_RTC_BUS_NUM 0x01
  175. #define CONFIG_SYS_I2C_RTC_ADDR 0x32
  176. /* Pass Ethernet MAC to VxWorks */
  177. #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
  178. #undef CONFIG_WATCHDOG /* watchdog disabled */
  179. /*
  180. * Miscellaneous configurable options
  181. */
  182. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  183. /*
  184. * For booting Linux, the board info and command line data
  185. * have to be in the first 256 MB of memory, since this is
  186. * the maximum mapped by the Linux kernel during initialization.
  187. */
  188. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
  189. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  190. /* System IO Config */
  191. #define CONFIG_SYS_SICRH 0
  192. #define CONFIG_SYS_SICRL SICRL_LDP_A
  193. #define CONFIG_SYS_GPIO1_PRELIM
  194. #define CONFIG_SYS_GPIO1_DIR 0x00100000
  195. #define CONFIG_SYS_GPIO1_DAT 0x00100000
  196. #define CONFIG_SYS_GPIO2_PRELIM
  197. #define CONFIG_SYS_GPIO2_DIR 0x78900000
  198. #define CONFIG_SYS_GPIO2_DAT 0x70100000
  199. #ifdef CONFIG_PCI
  200. #define CONFIG_PCI_INDIRECT_BRIDGE
  201. #endif
  202. #if defined(CONFIG_CMD_KGDB)
  203. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  204. #endif
  205. /*
  206. * Environment Configuration
  207. */
  208. #define CONFIG_ENV_OVERWRITE
  209. #if defined(CONFIG_TSEC_ENET)
  210. #define CONFIG_HAS_ETH0
  211. #define CONFIG_HAS_ETH1
  212. #endif
  213. #define CONFIG_HOSTNAME "VME8349"
  214. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  215. #define CONFIG_BOOTFILE "uImage"
  216. #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
  217. #define CONFIG_EXTRA_ENV_SETTINGS \
  218. "netdev=eth0\0" \
  219. "hostname=vme8349\0" \
  220. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  221. "nfsroot=${serverip}:${rootpath}\0" \
  222. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  223. "addip=setenv bootargs ${bootargs} " \
  224. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  225. ":${hostname}:${netdev}:off panic=1\0" \
  226. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  227. "flash_nfs=run nfsargs addip addtty;" \
  228. "bootm ${kernel_addr}\0" \
  229. "flash_self=run ramargs addip addtty;" \
  230. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  231. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  232. "bootm\0" \
  233. "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
  234. "update=protect off fff00000 fff3ffff; " \
  235. "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
  236. "upd=run load update\0" \
  237. "fdtaddr=780000\0" \
  238. "fdtfile=vme8349.dtb\0" \
  239. ""
  240. #define CONFIG_NFSBOOTCOMMAND \
  241. "setenv bootargs root=/dev/nfs rw " \
  242. "nfsroot=$serverip:$rootpath " \
  243. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  244. "$netdev:off " \
  245. "console=$consoledev,$baudrate $othbootargs;" \
  246. "tftp $loadaddr $bootfile;" \
  247. "tftp $fdtaddr $fdtfile;" \
  248. "bootm $loadaddr - $fdtaddr"
  249. #define CONFIG_RAMBOOTCOMMAND \
  250. "setenv bootargs root=/dev/ram rw " \
  251. "console=$consoledev,$baudrate $othbootargs;" \
  252. "tftp $ramdiskaddr $ramdiskfile;" \
  253. "tftp $loadaddr $bootfile;" \
  254. "tftp $fdtaddr $fdtfile;" \
  255. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  256. #define CONFIG_BOOTCOMMAND "run flash_self"
  257. #ifndef __ASSEMBLY__
  258. int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
  259. unsigned char *buffer, int len);
  260. #endif
  261. #endif /* __CONFIG_H */