vexpress_aemv8a.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration for Versatile Express. Parts were derived from other ARM
  4. * configurations.
  5. */
  6. #ifndef __VEXPRESS_AEMV8A_H
  7. #define __VEXPRESS_AEMV8A_H
  8. #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  9. #ifndef CONFIG_SEMIHOSTING
  10. #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
  11. #endif
  12. #endif
  13. #define CONFIG_REMAKE_ELF
  14. /* Link Definitions */
  15. #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  16. /* ATF loads u-boot here for BASE_FVP model */
  17. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  18. #elif CONFIG_TARGET_VEXPRESS64_JUNO
  19. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  20. #endif
  21. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  22. /* CS register bases for the original memory map. */
  23. #define V2M_PA_CS0 0x00000000
  24. #define V2M_PA_CS1 0x14000000
  25. #define V2M_PA_CS2 0x18000000
  26. #define V2M_PA_CS3 0x1c000000
  27. #define V2M_PA_CS4 0x0c000000
  28. #define V2M_PA_CS5 0x10000000
  29. #define V2M_PERIPH_OFFSET(x) (x << 16)
  30. #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  31. #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  32. #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  33. #define V2M_BASE 0x80000000
  34. /* Common peripherals relative to CS7. */
  35. #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  36. #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  37. #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  38. #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  39. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  40. #define V2M_UART0 0x7ff80000
  41. #define V2M_UART1 0x7ff70000
  42. #else /* Not Juno */
  43. #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  44. #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  45. #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  46. #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  47. #endif
  48. #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  49. #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  50. #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  51. #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  52. #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  53. #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  54. #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  55. /* System register offsets. */
  56. #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
  57. #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
  58. #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
  59. /* Generic Timer Definitions */
  60. #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
  61. /* Generic Interrupt Controller Definitions */
  62. #ifdef CONFIG_GICV3
  63. #define GICD_BASE (0x2f000000)
  64. #define GICR_BASE (0x2f100000)
  65. #else
  66. #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  67. #define GICD_BASE (0x2f000000)
  68. #define GICC_BASE (0x2c000000)
  69. #elif CONFIG_TARGET_VEXPRESS64_JUNO
  70. #define GICD_BASE (0x2C010000)
  71. #define GICC_BASE (0x2C02f000)
  72. #endif
  73. #endif /* !CONFIG_GICV3 */
  74. /* Size of malloc() pool */
  75. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
  76. #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
  77. /* The Vexpress64 simulators use SMSC91C111 */
  78. #define CONFIG_SMC91111 1
  79. #define CONFIG_SMC91111_BASE (0x01A000000)
  80. #endif
  81. /* PL011 Serial Configuration */
  82. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  83. #define CONFIG_PL011_CLOCK 7273800
  84. #else
  85. #define CONFIG_PL011_CLOCK 24000000
  86. #endif
  87. /* BOOTP options */
  88. #define CONFIG_BOOTP_BOOTFILESIZE
  89. /* Miscellaneous configurable options */
  90. #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
  91. /* Physical Memory Map */
  92. #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
  93. /* Top 16MB reserved for secure world use */
  94. #define DRAM_SEC_SIZE 0x01000000
  95. #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
  96. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  97. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  98. #define PHYS_SDRAM_2 (0x880000000)
  99. #define PHYS_SDRAM_2_SIZE 0x180000000
  100. #endif
  101. /* Enable memtest */
  102. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
  103. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
  104. /* Initial environment variables */
  105. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  106. /*
  107. * Defines where the kernel and FDT exist in NOR flash and where it will
  108. * be copied into DRAM
  109. */
  110. #define CONFIG_EXTRA_ENV_SETTINGS \
  111. "kernel_name=norkern\0" \
  112. "kernel_alt_name=Image\0" \
  113. "kernel_addr=0x80080000\0" \
  114. "initrd_name=ramdisk.img\0" \
  115. "initrd_addr=0x84000000\0" \
  116. "fdtfile=board.dtb\0" \
  117. "fdt_alt_name=juno\0" \
  118. "fdt_addr=0x83000000\0" \
  119. "fdt_high=0xffffffffffffffff\0" \
  120. "initrd_high=0xffffffffffffffff\0" \
  121. /* Copy the kernel and FDT to DRAM memory and boot */
  122. #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
  123. "if test $? -eq 1; then "\
  124. " echo Loading ${kernel_alt_name} instead of "\
  125. "${kernel_name}; "\
  126. " afs load ${kernel_alt_name} ${kernel_addr};"\
  127. "fi ; "\
  128. "afs load ${fdtfile} ${fdt_addr} ; " \
  129. "if test $? -eq 1; then "\
  130. " echo Loading ${fdt_alt_name} instead of "\
  131. "${fdtfile}; "\
  132. " afs load ${fdt_alt_name} ${fdt_addr}; "\
  133. "fi ; "\
  134. "fdt addr ${fdt_addr}; fdt resize; " \
  135. "if afs load ${initrd_name} ${initrd_addr} ; "\
  136. "then "\
  137. " setenv initrd_param ${initrd_addr}; "\
  138. " else setenv initrd_param -; "\
  139. "fi ; " \
  140. "booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
  141. #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
  142. #define CONFIG_EXTRA_ENV_SETTINGS \
  143. "kernel_name=Image\0" \
  144. "kernel_addr=0x80080000\0" \
  145. "initrd_name=ramdisk.img\0" \
  146. "initrd_addr=0x88000000\0" \
  147. "fdtfile=devtree.dtb\0" \
  148. "fdt_addr=0x83000000\0" \
  149. "fdt_high=0xffffffffffffffff\0" \
  150. "initrd_high=0xffffffffffffffff\0"
  151. #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
  152. "smhload ${fdtfile} ${fdt_addr}; " \
  153. "smhload ${initrd_name} ${initrd_addr} "\
  154. "initrd_end; " \
  155. "fdt addr ${fdt_addr}; fdt resize; " \
  156. "fdt chosen ${initrd_addr} ${initrd_end}; " \
  157. "booti $kernel_addr - $fdt_addr"
  158. #endif
  159. /* Monitor Command Prompt */
  160. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  161. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  162. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  163. #define CONFIG_SYS_FLASH_BASE 0x08000000
  164. /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
  165. #define CONFIG_SYS_MAX_FLASH_SECT 259
  166. /* Store environment at top of flash in the same location as blank.img */
  167. /* in the Juno firmware. */
  168. #else
  169. #define CONFIG_SYS_FLASH_BASE 0x0C000000
  170. /* 256 x 256KiB sectors */
  171. #define CONFIG_SYS_MAX_FLASH_SECT 256
  172. /* Store environment at top of flash */
  173. #endif
  174. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  175. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  176. #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
  177. #define FLASH_MAX_SECTOR_SIZE 0x00040000
  178. #endif /* __VEXPRESS_AEMV8A_H */