trats.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Samsung Electronics
  4. * Heungjun Kim <riverful.kim@samsung.com>
  5. *
  6. * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
  7. */
  8. #ifndef __CONFIG_TRATS_H
  9. #define __CONFIG_TRATS_H
  10. #include <configs/exynos4-common.h>
  11. #define CONFIG_TRATS
  12. #define CONFIG_TIZEN /* TIZEN lib */
  13. #define CONFIG_SYS_L2CACHE_OFF
  14. #ifndef CONFIG_SYS_L2CACHE_OFF
  15. #define CONFIG_SYS_L2_PL310
  16. #define CONFIG_SYS_PL310_BASE 0x10502000
  17. #endif
  18. /* TRATS has 4 banks of DRAM */
  19. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  20. #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  21. #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
  22. /* memtest works on */
  23. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  24. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
  25. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
  26. /* select serial console configuration */
  27. #define CONFIG_MACH_TYPE MACH_TYPE_TRATS
  28. #define CONFIG_BOOTCOMMAND "run autoboot"
  29. #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
  30. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
  31. - GENERATED_GBL_DATA_SIZE)
  32. #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
  33. #define CONFIG_SYS_MONITOR_BASE 0x00000000
  34. #define CONFIG_BOOTBLOCK "10"
  35. #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
  36. #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
  37. #define CONFIG_ENV_OVERWRITE
  38. /* Tizen - partitions definitions */
  39. #define PARTS_CSA "csa-mmc"
  40. #define PARTS_BOOT "boot"
  41. #define PARTS_QBOOT "qboot"
  42. #define PARTS_CSC "csc"
  43. #define PARTS_ROOT "platform"
  44. #define PARTS_DATA "data"
  45. #define PARTS_UMS "ums"
  46. #define PARTS_DEFAULT \
  47. "uuid_disk=${uuid_gpt_disk};" \
  48. "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
  49. "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
  50. "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
  51. "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
  52. "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
  53. "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
  54. "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
  55. #define CONFIG_DFU_ALT \
  56. "u-boot raw 0x80 0x400;" \
  57. "/uImage ext4 0 2;" \
  58. "/modem.bin ext4 0 2;" \
  59. "/exynos4210-trats.dtb ext4 0 2;" \
  60. ""PARTS_CSA" part 0 1;" \
  61. ""PARTS_BOOT" part 0 2;" \
  62. ""PARTS_QBOOT" part 0 3;" \
  63. ""PARTS_CSC" part 0 4;" \
  64. ""PARTS_ROOT" part 0 5;" \
  65. ""PARTS_DATA" part 0 6;" \
  66. ""PARTS_UMS" part 0 7;" \
  67. "params.bin raw 0x38 0x8;" \
  68. "/Image.itb ext4 0 2\0"
  69. #define CONFIG_EXTRA_ENV_SETTINGS \
  70. "bootk=" \
  71. "run loaduimage;" \
  72. "if run loaddtb; then " \
  73. "bootm 0x40007FC0 - ${fdtaddr};" \
  74. "fi;" \
  75. "bootm 0x40007FC0;\0" \
  76. "updatebackup=" \
  77. "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
  78. "mmc dev 0 0\0" \
  79. "updatebootb=" \
  80. "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
  81. "lpj=lpj=3981312\0" \
  82. "nfsboot=" \
  83. "setenv bootargs root=/dev/nfs rw " \
  84. "nfsroot=${nfsroot},nolock,tcp " \
  85. "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  86. "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
  87. "; run bootk\0" \
  88. "ramfsboot=" \
  89. "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
  90. "${console} ${meminfo} " \
  91. "initrd=0x43000000,8M ramdisk=8192\0" \
  92. "mmcboot=" \
  93. "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
  94. "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
  95. "run bootk\0" \
  96. "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
  97. "boottrace=setenv opts initcall_debug; run bootcmd\0" \
  98. "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
  99. "verify=n\0" \
  100. "rootfstype=ext4\0" \
  101. "console=" CONFIG_DEFAULT_CONSOLE \
  102. "meminfo=crashkernel=32M@0x50000000\0" \
  103. "nfsroot=/nfsroot/arm\0" \
  104. "bootblock=" CONFIG_BOOTBLOCK "\0" \
  105. "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
  106. "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
  107. "${fdtfile}\0" \
  108. "mmcdev=0\0" \
  109. "mmcbootpart=2\0" \
  110. "mmcrootpart=5\0" \
  111. "opts=always_resume=1\0" \
  112. "partitions=" PARTS_DEFAULT \
  113. "dfu_alt_info=" CONFIG_DFU_ALT \
  114. "spladdr=0x40000100\0" \
  115. "splsize=0x200\0" \
  116. "splfile=falcon.bin\0" \
  117. "spl_export=" \
  118. "setexpr spl_imgsize ${splsize} + 8 ;" \
  119. "setenv spl_imgsize 0x${spl_imgsize};" \
  120. "setexpr spl_imgaddr ${spladdr} - 8 ;" \
  121. "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
  122. "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
  123. "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
  124. "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
  125. "spl export atags 0x40007FC0;" \
  126. "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
  127. "mw.l ${spl_addr_tmp} ${splsize};" \
  128. "ext4write mmc ${mmcdev}:${mmcbootpart}" \
  129. " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
  130. "setenv spl_imgsize;" \
  131. "setenv spl_imgaddr;" \
  132. "setenv spl_addr_tmp;\0" \
  133. CONFIG_EXTRA_ENV_ITB \
  134. "fdtaddr=40800000\0" \
  135. /* Falcon mode definitions */
  136. #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
  137. /* GPT */
  138. /* Security subsystem - enable hw_rand() */
  139. #define CONFIG_EXYNOS_ACE_SHA
  140. /* Common misc for Samsung */
  141. #define CONFIG_MISC_COMMON
  142. /* Download menu - Samsung common */
  143. #define CONFIG_LCD_MENU
  144. /* Download menu - definitions for check keys */
  145. #ifndef __ASSEMBLY__
  146. #define KEY_PWR_PMIC_NAME "MAX8997_PMIC"
  147. #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1
  148. #define KEY_PWR_STATUS_MASK (1 << 0)
  149. #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
  150. #define KEY_PWR_INTERRUPT_MASK (1 << 0)
  151. #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
  152. #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
  153. #endif /* __ASSEMBLY__ */
  154. /* LCD console */
  155. #define LCD_BPP LCD_COLOR16
  156. /* LCD */
  157. #define CONFIG_BMP_16BPP
  158. #define CONFIG_FB_ADDR 0x52504000
  159. #define CONFIG_EXYNOS_MIPI_DSIM
  160. #define CONFIG_VIDEO_BMP_GZIP
  161. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
  162. #endif /* __CONFIG_H */