tegra30-common.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010-2012
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _TEGRA30_COMMON_H_
  7. #define _TEGRA30_COMMON_H_
  8. #include "tegra-common.h"
  9. /*
  10. * NS16550 Configuration
  11. */
  12. #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
  13. /*
  14. * Miscellaneous configurable options
  15. */
  16. #define CONFIG_STACKBASE 0x83800000 /* 56MB */
  17. /*
  18. * Memory layout for where various images get loaded by boot scripts:
  19. *
  20. * scriptaddr can be pretty much anywhere that doesn't conflict with something
  21. * else. Put it above BOOTMAPSZ to eliminate conflicts.
  22. *
  23. * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  24. * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  25. *
  26. * kernel_addr_r must be within the first 128M of RAM in order for the
  27. * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  28. * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  29. * should not overlap that area, or the kernel will have to copy itself
  30. * somewhere else before decompression. Similarly, the address of any other
  31. * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  32. * this up to 32M allows for a sizable kernel to be decompressed below the
  33. * compressed load address.
  34. *
  35. * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
  36. * the compressed kernel to be up to 32M too.
  37. *
  38. * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  39. * for the FDT/DTB to be up to 1M, which is hopefully plenty.
  40. */
  41. #define CONFIG_LOADADDR 0x81000000
  42. #define MEM_LAYOUT_ENV_SETTINGS \
  43. "scriptaddr=0x90000000\0" \
  44. "pxefile_addr_r=0x90100000\0" \
  45. "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  46. "fdt_addr_r=0x83000000\0" \
  47. "ramdisk_addr_r=0x83100000\0"
  48. /* Defines for SPL */
  49. #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
  50. #define CONFIG_SPL_STACK 0x800ffffc
  51. /* For USB EHCI controller */
  52. #define CONFIG_EHCI_IS_TDI
  53. #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
  54. #endif /* _TEGRA30_COMMON_H_ */