tao3530.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the TechNexion TAO-3530 SOM
  4. * equipped on Thunder baseboard.
  5. *
  6. * Edward Lin <linuxfae@technexion.com>
  7. * Tapani Utriainen <linuxfae@technexion.com>
  8. *
  9. * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. */
  16. #include <asm/arch/cpu.h> /* get chip and board defs */
  17. #include <asm/arch/omap.h>
  18. /* Clock Defines */
  19. #define V_OSCK 26000000 /* Clock output from T2 */
  20. #define V_SCLK (V_OSCK >> 1)
  21. #define CONFIG_CMDLINE_TAG
  22. #define CONFIG_SETUP_MEMORY_TAGS
  23. #define CONFIG_INITRD_TAG
  24. #define CONFIG_REVISION_TAG
  25. /*
  26. * Size of malloc() pool
  27. */
  28. #define CONFIG_SYS_MALLOC_LEN (4 << 20)
  29. /*
  30. * Hardware drivers
  31. */
  32. /*
  33. * NS16550 Configuration
  34. */
  35. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  36. #define CONFIG_SYS_NS16550_SERIAL
  37. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  38. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  39. /*
  40. * select serial console configuration
  41. */
  42. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  43. /* allow to overwrite serial and ethaddr */
  44. #define CONFIG_ENV_OVERWRITE
  45. /* commands to include */
  46. #define CONFIG_SYS_I2C
  47. #define CONFIG_I2C_MULTI_BUS
  48. /*
  49. * TWL4030
  50. */
  51. /*
  52. * Board NAND Info.
  53. */
  54. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  55. /* to access nand at */
  56. /* CS0 */
  57. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  58. /* devices */
  59. /* Environment information */
  60. #define CONFIG_EXTRA_ENV_SETTINGS \
  61. "loadaddr=0x82000000\0" \
  62. "console=ttyO2,115200n8\0" \
  63. "mpurate=600\0" \
  64. "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
  65. "tv_mode=omapfb.mode=tv:ntsc\0" \
  66. "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
  67. "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
  68. "extra_options= \0" \
  69. "mmcdev=0\0" \
  70. "mmcroot=/dev/mmcblk0p2 rw\0" \
  71. "mmcrootfstype=ext3 rootwait\0" \
  72. "nandroot=ubi0:rootfs ubi.mtd=4\0" \
  73. "nandrootfstype=ubifs\0" \
  74. "mmcargs=setenv bootargs console=${console} " \
  75. "mpurate=${mpurate} " \
  76. "${video_mode} " \
  77. "root=${mmcroot} " \
  78. "rootfstype=${mmcrootfstype} " \
  79. "${extra_options}\0" \
  80. "nandargs=setenv bootargs console=${console} " \
  81. "mpurate=${mpurate} " \
  82. "${video_mode} " \
  83. "${network_setting} " \
  84. "root=${nandroot} " \
  85. "rootfstype=${nandrootfstype} "\
  86. "${extra_options}\0" \
  87. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  88. "bootscript=echo Running bootscript from mmc ...; " \
  89. "source ${loadaddr}\0" \
  90. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  91. "mmcboot=echo Booting from mmc ...; " \
  92. "run mmcargs; " \
  93. "bootm ${loadaddr}\0" \
  94. "nandboot=echo Booting from nand ...; " \
  95. "run nandargs; " \
  96. "nand read ${loadaddr} 280000 400000; " \
  97. "bootm ${loadaddr}\0" \
  98. #define CONFIG_BOOTCOMMAND \
  99. "mmc dev ${mmcdev}; if mmc rescan; then " \
  100. "if run loadbootscript; then " \
  101. "run bootscript; " \
  102. "else " \
  103. "if run loaduimage; then " \
  104. "run mmcboot; " \
  105. "else run nandboot; " \
  106. "fi; " \
  107. "fi; " \
  108. "else run nandboot; fi"
  109. /*
  110. * Miscellaneous configurable options
  111. */
  112. /* turn on command-line edit/hist/auto */
  113. #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
  114. /* defaults */
  115. #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
  116. #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
  117. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  118. /* load address */
  119. /*
  120. * OMAP3 has 12 GP timers, they can be driven by the system clock
  121. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  122. * This rate is divided by a local divisor.
  123. */
  124. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  125. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  126. /*
  127. * Physical Memory Map
  128. */
  129. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  130. #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
  131. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  132. /*
  133. * FLASH and environment organization
  134. */
  135. /* **** PISMO SUPPORT *** */
  136. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  137. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  138. /* Monitor at start of flash */
  139. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  140. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  141. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  142. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
  143. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  144. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  145. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  146. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  147. CONFIG_SYS_INIT_RAM_SIZE - \
  148. GENERATED_GBL_DATA_SIZE)
  149. /*
  150. * USB
  151. *
  152. * Currently only EHCI is enabled, the MUSB OTG controller
  153. * is not enabled.
  154. */
  155. /* USB EHCI */
  156. #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
  157. /* Defines for SPL */
  158. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  159. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  160. #define CONFIG_SPL_NAND_BASE
  161. #define CONFIG_SPL_NAND_DRIVERS
  162. #define CONFIG_SPL_NAND_ECC
  163. /* NAND boot config */
  164. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  165. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  166. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  167. #define CONFIG_SYS_NAND_OOBSIZE 64
  168. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  169. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  170. /*
  171. * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
  172. * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
  173. */
  174. #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  175. 10, 11, 12, 13 }
  176. #define CONFIG_SYS_NAND_ECCSIZE 512
  177. #define CONFIG_SYS_NAND_ECCBYTES 3
  178. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  179. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  180. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  181. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  182. CONFIG_SPL_TEXT_BASE)
  183. /*
  184. * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
  185. * older x-loader implementations. And move the BSS area so that it
  186. * doesn't overlap with TEXT_BASE.
  187. */
  188. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  189. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  190. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  191. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  192. #endif /* __CONFIG_H */