tam3517-common.h 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011
  4. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  5. *
  6. * Copyright (C) 2009 TechNexion Ltd.
  7. */
  8. #ifndef __TAM3517_H
  9. #define __TAM3517_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #include <asm/arch/cpu.h> /* get chip and board defs */
  14. #include <asm/arch/omap.h>
  15. /* Clock Defines */
  16. #define V_OSCK 26000000 /* Clock output from T2 */
  17. #define V_SCLK (V_OSCK >> 1)
  18. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  19. #define CONFIG_SETUP_MEMORY_TAGS
  20. #define CONFIG_INITRD_TAG
  21. #define CONFIG_REVISION_TAG
  22. /*
  23. * Size of malloc() pool
  24. */
  25. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
  26. 2 * 1024 * 1024)
  27. /*
  28. * DDR related
  29. */
  30. #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
  31. /*
  32. * Hardware drivers
  33. */
  34. /*
  35. * NS16550 Configuration
  36. */
  37. #define CONFIG_SYS_NS16550_SERIAL
  38. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  39. #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  40. /*
  41. * select serial console configuration
  42. */
  43. #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
  44. /* allow to overwrite serial and ethaddr */
  45. #define CONFIG_ENV_OVERWRITE
  46. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  47. 115200}
  48. /* EHCI */
  49. #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
  50. #define CONFIG_SYS_I2C
  51. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
  52. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  53. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  54. /*
  55. * Board NAND Info.
  56. */
  57. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  58. /* to access */
  59. /* nand at CS0 */
  60. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  61. /* NAND devices */
  62. /*
  63. * Miscellaneous configurable options
  64. */
  65. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  66. #define CONFIG_SYS_MAXARGS 32 /* max number of command */
  67. /* args */
  68. /* memtest works on */
  69. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  70. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  71. 0x01F00000) /* 31MB */
  72. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
  73. /* address */
  74. /*
  75. * AM3517 has 12 GP timers, they can be driven by the system clock
  76. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  77. * This rate is divided by a local divisor.
  78. */
  79. #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
  80. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  81. /*
  82. * Physical Memory Map
  83. */
  84. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  85. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  86. /*
  87. * FLASH and environment organization
  88. */
  89. /* **** PISMO SUPPORT *** */
  90. /* Redundant Environment */
  91. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
  92. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  93. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  94. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  95. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  96. CONFIG_SYS_INIT_RAM_SIZE - \
  97. GENERATED_GBL_DATA_SIZE)
  98. /*
  99. * ethernet support, EMAC
  100. *
  101. */
  102. #define CONFIG_DRIVER_TI_EMAC_USE_RMII
  103. #define CONFIG_BOOTP_DNS2
  104. #define CONFIG_BOOTP_SEND_HOSTNAME
  105. #define CONFIG_NET_RETRY_COUNT 10
  106. /* Defines for SPL */
  107. #define CONFIG_SPL_CONSOLE
  108. #define CONFIG_SPL_NAND_SOFTECC
  109. #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
  110. #define CONFIG_SPL_NAND_BASE
  111. #define CONFIG_SPL_NAND_DRIVERS
  112. #define CONFIG_SPL_NAND_ECC
  113. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  114. CONFIG_SPL_TEXT_BASE)
  115. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  116. #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
  117. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  118. #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
  119. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  120. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  121. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  122. /* FAT */
  123. #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
  124. #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
  125. /* RAW SD card / eMMC */
  126. #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
  127. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
  128. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
  129. /* NAND boot config */
  130. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  131. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  132. #define CONFIG_SYS_NAND_OOBSIZE 64
  133. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  134. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  135. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  136. #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
  137. 48, 49, 50, 51, 52, 53, 54, 55,\
  138. 56, 57, 58, 59, 60, 61, 62, 63}
  139. #define CONFIG_SYS_NAND_ECCSIZE 256
  140. #define CONFIG_SYS_NAND_ECCBYTES 3
  141. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
  142. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  143. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  144. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
  145. /* Setup MTD for NAND on the SOM */
  146. #define CONFIG_TAM3517_SETTINGS \
  147. "netdev=eth0\0" \
  148. "nandargs=setenv bootargs root=${nandroot} " \
  149. "rootfstype=${nandrootfstype}\0" \
  150. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  151. "nfsroot=${serverip}:${rootpath}\0" \
  152. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  153. "addip_sta=setenv bootargs ${bootargs} " \
  154. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  155. ":${hostname}:${netdev}:off panic=1\0" \
  156. "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
  157. "addip=if test -n ${ipdyn};then run addip_dyn;" \
  158. "else run addip_sta;fi\0" \
  159. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  160. "addtty=setenv bootargs ${bootargs}" \
  161. " console=ttyO0,${baudrate}\0" \
  162. "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
  163. "loadaddr=82000000\0" \
  164. "kernel_addr_r=82000000\0" \
  165. "hostname=" CONFIG_HOSTNAME "\0" \
  166. "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
  167. "flash_self=run ramargs addip addtty addmtd addmisc;" \
  168. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  169. "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
  170. "bootm ${kernel_addr}\0" \
  171. "nandboot=run nandargs addip addtty addmtd addmisc;" \
  172. "nand read ${kernel_addr_r} kernel\0" \
  173. "bootm ${kernel_addr_r}\0" \
  174. "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  175. "run nfsargs addip addtty addmtd addmisc;" \
  176. "bootm ${kernel_addr_r}\0" \
  177. "net_self=if run net_self_load;then " \
  178. "run ramargs addip addtty addmtd addmisc;" \
  179. "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
  180. "else echo Images not loades;fi\0" \
  181. "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
  182. "load=tftp ${loadaddr} ${u-boot}\0" \
  183. "loadmlo=tftp ${loadaddr} ${mlo}\0" \
  184. "mlo=" CONFIG_HOSTNAME "/MLO\0" \
  185. "uboot_addr=0x80000\0" \
  186. "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
  187. "nand write ${loadaddr} ${uboot_addr} 80000\0" \
  188. "updatemlo=nandecc hw;nand erase 0 20000;" \
  189. "nand write ${loadaddr} 0 20000\0" \
  190. "upd=if run load;then echo Updating u-boot;if run update;" \
  191. "then echo U-Boot updated;" \
  192. "else echo Error updating u-boot !;" \
  193. "echo Board without bootloader !!;" \
  194. "fi;" \
  195. "else echo U-Boot not downloaded..exiting;fi\0" \
  196. /*
  197. * this is common code for all TAM3517 boards.
  198. * MAC address is stored from manufacturer in
  199. * I2C EEPROM
  200. */
  201. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  202. /*
  203. * The I2C EEPROM on the TAM3517 contains
  204. * mac address and production data
  205. */
  206. struct tam3517_module_info {
  207. char customer[48];
  208. char product[48];
  209. /*
  210. * bit 0~47 : sequence number
  211. * bit 48~55 : week of year, from 0.
  212. * bit 56~63 : year
  213. */
  214. unsigned long long sequence_number;
  215. /*
  216. * bit 0~7 : revision fixed
  217. * bit 8~15 : revision major
  218. * bit 16~31 : TNxxx
  219. */
  220. unsigned int revision;
  221. unsigned char eth_addr[4][8];
  222. unsigned char _rev[100];
  223. };
  224. #define TAM3517_READ_EEPROM(info, ret) \
  225. do { \
  226. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
  227. if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
  228. (void *)info, sizeof(*info))) \
  229. ret = 1; \
  230. else \
  231. ret = 0; \
  232. } while (0)
  233. #define TAM3517_READ_MAC_FROM_EEPROM(info) \
  234. do { \
  235. char buf[80], ethname[20]; \
  236. int i; \
  237. memset(buf, 0, sizeof(buf)); \
  238. for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
  239. sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
  240. (info)->eth_addr[i][5], \
  241. (info)->eth_addr[i][4], \
  242. (info)->eth_addr[i][3], \
  243. (info)->eth_addr[i][2], \
  244. (info)->eth_addr[i][1], \
  245. (info)->eth_addr[i][0]); \
  246. \
  247. if (i) \
  248. sprintf(ethname, "eth%daddr", i); \
  249. else \
  250. strcpy(ethname, "ethaddr"); \
  251. printf("Setting %s from EEPROM with %s\n", ethname, buf);\
  252. env_set(ethname, buf); \
  253. } \
  254. } while (0)
  255. /* The following macros are taken from Technexion's documentation */
  256. #define TAM3517_sequence_number(info) \
  257. ((info)->sequence_number % 0x1000000000000LL)
  258. #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
  259. #define TAM3517_year(info) ((info)->sequence_number >> 56)
  260. #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
  261. #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
  262. #define TAM3517_revision_tn(info) ((info)->revision >> 16)
  263. #define TAM3517_PRINT_SOM_INFO(info) \
  264. do { \
  265. printf("Vendor:%s\n", (info)->customer); \
  266. printf("SOM: %s\n", (info)->product); \
  267. printf("SeqNr: %02llu%02llu%012llu\n", \
  268. TAM3517_year(info), \
  269. TAM3517_week_of_year(info), \
  270. TAM3517_sequence_number(info)); \
  271. printf("Rev: TN%u %u.%u\n", \
  272. TAM3517_revision_tn(info), \
  273. TAM3517_revision_major(info), \
  274. TAM3517_revision_fixed(info)); \
  275. } while (0)
  276. #endif
  277. #endif /* __TAM3517_H */