socfpga_stratix10_socdk.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef __CONFIG_SOCFGPA_STRATIX10_H__
  7. #define __CONFIG_SOCFGPA_STRATIX10_H__
  8. #include <asm/arch/base_addr_s10.h>
  9. #include <asm/arch/handoff_s10.h>
  10. /*
  11. * U-Boot general configurations
  12. */
  13. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_LOADADDR 0x2000000
  15. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  16. #define CONFIG_REMAKE_ELF
  17. /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18. #define CPU_RELEASE_ADDR 0xFFD12210
  19. #define CONFIG_SYS_CACHELINE_SIZE 64
  20. #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
  21. /*
  22. * U-Boot console configurations
  23. */
  24. #define CONFIG_SYS_MAXARGS 64
  25. #define CONFIG_SYS_CBSIZE 2048
  26. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  27. sizeof(CONFIG_SYS_PROMPT) + 16)
  28. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  29. /* Extend size of kernel image for uncompression */
  30. #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
  31. /*
  32. * U-Boot run time memory configurations
  33. */
  34. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  35. #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
  36. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
  37. + CONFIG_SYS_INIT_RAM_SIZE \
  38. - S10_HANDOFF_SIZE)
  39. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
  40. #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
  41. /*
  42. * U-Boot environment configurations
  43. */
  44. #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
  45. /*
  46. * QSPI support
  47. */
  48. #ifdef CONFIG_CADENCE_QSPI
  49. /* Enable it if you want to use dual-stacked mode */
  50. /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
  51. /* Flash device info */
  52. /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  53. #ifndef CONFIG_SPL_BUILD
  54. #define CONFIG_MTD_PARTITIONS
  55. #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
  56. #endif /* CONFIG_SPL_BUILD */
  57. #ifndef __ASSEMBLY__
  58. unsigned int cm_get_qspi_controller_clk_hz(void);
  59. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  60. #endif
  61. #endif /* CONFIG_CADENCE_QSPI */
  62. /*
  63. * Boot arguments passed to the boot command. The value of
  64. * CONFIG_BOOTARGS goes into the environment value "bootargs".
  65. * Do note the value will override also the chosen node in FDT blob.
  66. */
  67. #define CONFIG_BOOTARGS "earlycon"
  68. #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
  69. "run mmcboot"
  70. #define CONFIG_EXTRA_ENV_SETTINGS \
  71. "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  72. "bootfile=Image\0" \
  73. "fdt_addr=8000000\0" \
  74. "fdtimage=socfpga_stratix10_socdk.dtb\0" \
  75. "mmcroot=/dev/mmcblk0p2\0" \
  76. "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  77. " root=${mmcroot} rw rootwait;" \
  78. "booti ${loadaddr} - ${fdt_addr}\0" \
  79. "mmcload=mmc rescan;" \
  80. "load mmc 0:1 ${loadaddr} ${bootfile};" \
  81. "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  82. "linux_qspi_enable=if sf probe; then " \
  83. "echo Enabling QSPI at Linux DTB...;" \
  84. "fdt addr ${fdt_addr}; fdt resize;" \
  85. "fdt set /soc/spi@ff8d2000 status okay;" \
  86. "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  87. " ${qspi_clock}; fi; \0" \
  88. "scriptaddr=0x02100000\0" \
  89. "scriptfile=u-boot.scr\0" \
  90. "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  91. "then source ${scriptaddr}; fi\0" \
  92. "socfpga_legacy_reset_compat=1\0"
  93. /*
  94. * Generic Interrupt Controller Definitions
  95. */
  96. #define CONFIG_GICV2
  97. /*
  98. * External memory configurations
  99. */
  100. #define PHYS_SDRAM_1 0x0
  101. #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
  102. #define CONFIG_SYS_SDRAM_BASE 0
  103. #define CONFIG_SYS_MEMTEST_START 0
  104. #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
  105. /*
  106. * Serial / UART configurations
  107. */
  108. #define CONFIG_SYS_NS16550_CLK 100000000
  109. #define CONFIG_SYS_NS16550_MEM32
  110. /*
  111. * Timer & watchdog configurations
  112. */
  113. #define COUNTER_FREQUENCY 400000000
  114. /*
  115. * SDMMC configurations
  116. */
  117. #ifdef CONFIG_CMD_MMC
  118. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  119. #endif
  120. /*
  121. * Flash configurations
  122. */
  123. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  124. /* Ethernet on SoC (EMAC) */
  125. #if defined(CONFIG_CMD_NET)
  126. #define CONFIG_DW_ALTDESCRIPTOR
  127. #endif /* CONFIG_CMD_NET */
  128. /*
  129. * L4 Watchdog
  130. */
  131. #ifdef CONFIG_SPL_BUILD
  132. #define CONFIG_HW_WATCHDOG
  133. #define CONFIG_DESIGNWARE_WATCHDOG
  134. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  135. #ifndef __ASSEMBLY__
  136. unsigned int cm_get_l4_sys_free_clk_hz(void);
  137. #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
  138. #endif
  139. #endif
  140. /*
  141. * SPL memory layout
  142. *
  143. * On chip RAM
  144. * 0xFFE0_0000 ...... Start of OCRAM
  145. * SPL code, rwdata
  146. * empty space
  147. * 0xFFEx_xxxx ...... Top of stack (grows down)
  148. * 0xFFEy_yyyy ...... Global Data
  149. * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
  150. * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
  151. * 0xFFE3_FFFF ...... End of OCRAM
  152. *
  153. * SDRAM
  154. * 0x0000_0000 ...... Start of SDRAM_1
  155. * unused / empty space for image loading
  156. * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
  157. * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
  158. * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
  159. *
  160. */
  161. #define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
  162. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  163. #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
  164. #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
  165. #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
  166. - CONFIG_SPL_BSS_MAX_SIZE)
  167. #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
  168. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
  169. - CONFIG_SYS_SPL_MALLOC_SIZE)
  170. /* SPL SDMMC boot support */
  171. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  172. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  173. #endif /* __CONFIG_H */