socfpga_common.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef __CONFIG_SOCFPGA_COMMON_H__
  6. #define __CONFIG_SOCFPGA_COMMON_H__
  7. /*
  8. * High level configuration
  9. */
  10. #define CONFIG_CLOCKS
  11. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  12. /*
  13. * Memory configurations
  14. */
  15. #define PHYS_SDRAM_1 0x0
  16. #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
  17. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
  18. #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
  19. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  20. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  21. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  22. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  23. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  24. /* SPL memory allocation configuration, this is for FAT implementation */
  25. #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  26. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
  27. #endif
  28. #define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
  29. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
  30. CONFIG_SYS_INIT_RAM_SIZE)
  31. #endif
  32. /*
  33. * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  34. * SRAM as bootcounter storage. Make sure to not put the stack directly
  35. * at this address to not overwrite the bootcounter by checking, if the
  36. * bootcounter address is located in the internal SRAM.
  37. */
  38. #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
  39. (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
  40. CONFIG_SYS_INIT_RAM_SIZE)))
  41. #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
  42. #else
  43. #define CONFIG_SPL_STACK \
  44. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  45. #endif
  46. /*
  47. * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  48. * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  49. * in U-Boot pre-reloc is higher than in SPL.
  50. */
  51. #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  52. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
  53. #else
  54. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
  55. #endif
  56. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  57. /*
  58. * U-Boot general configurations
  59. */
  60. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  61. /* Print buffer size */
  62. #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  63. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  64. /* Boot argument buffer size */
  65. /*
  66. * Cache
  67. */
  68. #define CONFIG_SYS_L2_PL310
  69. #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
  70. /*
  71. * Ethernet on SoC (EMAC)
  72. */
  73. #ifdef CONFIG_CMD_NET
  74. #define CONFIG_DW_ALTDESCRIPTOR
  75. #endif
  76. /*
  77. * FPGA Driver
  78. */
  79. #ifdef CONFIG_CMD_FPGA
  80. #define CONFIG_FPGA_COUNT 1
  81. #endif
  82. /*
  83. * L4 OSC1 Timer 0
  84. */
  85. #ifndef CONFIG_TIMER
  86. /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
  87. #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
  88. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  89. #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
  90. #define CONFIG_SYS_TIMER_RATE 25000000
  91. #endif
  92. /*
  93. * L4 Watchdog
  94. */
  95. #ifdef CONFIG_HW_WATCHDOG
  96. #define CONFIG_DESIGNWARE_WATCHDOG
  97. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  98. #define CONFIG_DW_WDT_CLOCK_KHZ 25000
  99. #endif
  100. /*
  101. * MMC Driver
  102. */
  103. #ifdef CONFIG_CMD_MMC
  104. /* FIXME */
  105. /* using smaller max blk cnt to avoid flooding the limited stack we have */
  106. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
  107. #endif
  108. /*
  109. * NAND Support
  110. */
  111. #ifdef CONFIG_NAND_DENALI
  112. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  113. #define CONFIG_SYS_NAND_ONFI_DETECTION
  114. #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
  115. #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
  116. #endif
  117. /*
  118. * QSPI support
  119. */
  120. /* QSPI reference clock */
  121. #ifndef __ASSEMBLY__
  122. unsigned int cm_get_qspi_controller_clk_hz(void);
  123. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  124. #endif
  125. /*
  126. * USB
  127. */
  128. /*
  129. * USB Gadget (DFU, UMS)
  130. */
  131. #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
  132. #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
  133. #define DFU_DEFAULT_POLL_TIMEOUT 300
  134. /* USB IDs */
  135. #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
  136. #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
  137. #endif
  138. /*
  139. * U-Boot environment
  140. */
  141. /* Environment for SDMMC boot */
  142. #if defined(CONFIG_ENV_IS_IN_MMC)
  143. #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
  144. #endif
  145. /* Environment for QSPI boot */
  146. /*
  147. * SPL
  148. *
  149. * SRAM Memory layout for gen 5:
  150. *
  151. * 0xFFFF_0000 ...... Start of SRAM
  152. * 0xFFFF_xxxx ...... Top of stack (grows down)
  153. * 0xFFFF_yyyy ...... Global Data
  154. * 0xFFFF_zzzz ...... Malloc area
  155. * 0xFFFF_FFFF ...... End of SRAM
  156. *
  157. * SRAM Memory layout for Arria 10:
  158. * 0xFFE0_0000 ...... Start of SRAM (bottom)
  159. * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
  160. * 0xFFEy_yyyy ...... Global Data
  161. * 0xFFEz_zzzz ...... Malloc area (grows up to top)
  162. * 0xFFE3_FFFF ...... End of SRAM (top)
  163. */
  164. #ifndef CONFIG_SPL_TEXT_BASE
  165. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  166. #endif
  167. /* SPL SDMMC boot support */
  168. #ifdef CONFIG_SPL_MMC_SUPPORT
  169. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  170. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  171. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  172. #endif
  173. #else
  174. #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
  175. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
  176. #endif
  177. #endif
  178. /* SPL QSPI boot support */
  179. /* SPL NAND boot support */
  180. #ifdef CONFIG_SPL_NAND_SUPPORT
  181. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  182. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  183. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  184. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
  185. #endif
  186. #endif
  187. /* Extra Environment */
  188. #ifndef CONFIG_SPL_BUILD
  189. #ifdef CONFIG_CMD_DHCP
  190. #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
  191. #else
  192. #define BOOT_TARGET_DEVICES_DHCP(func)
  193. #endif
  194. #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
  195. #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
  196. #else
  197. #define BOOT_TARGET_DEVICES_PXE(func)
  198. #endif
  199. #ifdef CONFIG_CMD_MMC
  200. #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
  201. #else
  202. #define BOOT_TARGET_DEVICES_MMC(func)
  203. #endif
  204. #define BOOT_TARGET_DEVICES(func) \
  205. BOOT_TARGET_DEVICES_MMC(func) \
  206. BOOT_TARGET_DEVICES_PXE(func) \
  207. BOOT_TARGET_DEVICES_DHCP(func)
  208. #include <config_distro_bootcmd.h>
  209. #ifndef CONFIG_EXTRA_ENV_SETTINGS
  210. #define CONFIG_EXTRA_ENV_SETTINGS \
  211. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  212. "bootm_size=0xa000000\0" \
  213. "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
  214. "fdt_addr_r=0x02000000\0" \
  215. "scriptaddr=0x02100000\0" \
  216. "pxefile_addr_r=0x02200000\0" \
  217. "ramdisk_addr_r=0x02300000\0" \
  218. "socfpga_legacy_reset_compat=1\0" \
  219. BOOTENV
  220. #endif
  221. #endif
  222. #endif /* __CONFIG_SOCFPGA_COMMON_H__ */