snapper9260.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Bluewater Systems Snapper 9260 and 9G20 modules
  4. *
  5. * (C) Copyright 2011 Bluewater Systems
  6. * Author: Andre Renaud <andre@bluewatersys.com>
  7. * Author: Ryan Mallon <ryan@bluewatersys.com>
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /* SoC type is defined in boards.cfg */
  12. #include <asm/hardware.h>
  13. #include <linux/sizes.h>
  14. /* ARM asynchronous clock */
  15. #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
  16. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  17. /* CPU */
  18. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  19. #define CONFIG_SETUP_MEMORY_TAGS
  20. #define CONFIG_INITRD_TAG
  21. #define CONFIG_SKIP_LOWLEVEL_INIT
  22. /* SDRAM */
  23. #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
  24. #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
  25. #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
  26. GENERATED_GBL_DATA_SIZE)
  27. /* Mem test settings */
  28. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  29. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
  30. /* NAND Flash */
  31. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  32. #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  33. #define CONFIG_SYS_NAND_DBW_8
  34. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
  35. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
  36. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  37. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
  38. /* Ethernet */
  39. #define CONFIG_MACB
  40. #define CONFIG_RMII
  41. #define CONFIG_NET_RETRY_COUNT 20
  42. #define CONFIG_RESET_PHY_R
  43. #define CONFIG_AT91_WANTS_COMMON_PHY
  44. #define CONFIG_TFTP_PORT
  45. #define CONFIG_TFTP_TSIZE
  46. /* USB */
  47. #define CONFIG_USB_ATMEL
  48. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  49. #define CONFIG_USB_OHCI_NEW
  50. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  51. #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
  52. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
  53. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  54. /* GPIOs and IO expander */
  55. #define CONFIG_ATMEL_LEGACY
  56. #define CONFIG_AT91_GPIO
  57. #define CONFIG_AT91_GPIO_PULLUP 1
  58. #define CONFIG_PCA953X
  59. #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
  60. #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
  61. /* UARTs/Serial console */
  62. #define CONFIG_ATMEL_USART
  63. #ifndef CONFIG_DM_SERIAL
  64. #define CONFIG_USART_BASE ATMEL_BASE_DBGU
  65. #define CONFIG_USART_ID ATMEL_ID_SYS
  66. #endif
  67. /* I2C - Bit-bashed */
  68. #define CONFIG_SYS_I2C
  69. #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  70. #define CONFIG_SYS_I2C_SOFT_SPEED 100000
  71. #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
  72. #define CONFIG_SOFT_I2C_READ_REPEATED_START
  73. #define I2C_INIT do { \
  74. at91_set_gpio_output(AT91_PIN_PA23, 1); \
  75. at91_set_gpio_output(AT91_PIN_PA24, 1); \
  76. at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
  77. at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
  78. } while (0)
  79. #define I2C_SOFT_DECLARATIONS
  80. #define I2C_ACTIVE
  81. #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
  82. #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
  83. #define I2C_SDA(bit) do { \
  84. if (bit) { \
  85. at91_set_gpio_input(AT91_PIN_PA23, 1); \
  86. } else { \
  87. at91_set_gpio_output(AT91_PIN_PA23, 1); \
  88. at91_set_gpio_value(AT91_PIN_PA23, bit); \
  89. } \
  90. } while (0)
  91. #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
  92. #define I2C_DELAY udelay(2)
  93. /* Boot options */
  94. #define CONFIG_SYS_LOAD_ADDR 0x23000000
  95. #define CONFIG_BOOTP_BOOTFILESIZE
  96. /* Environment settings */
  97. #define CONFIG_ENV_OVERWRITE
  98. /* Console settings */
  99. /* U-Boot memory settings */
  100. #define CONFIG_SYS_MALLOC_LEN (1 << 20)
  101. #endif /* __CONFIG_H */