sbc8641d.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007 Wind River Systems <www.windriver.com>
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. * Joe Hamman <joe.hamman@embeddedspecialties.com>
  6. *
  7. * Copyright 2006 Freescale Semiconductor.
  8. *
  9. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  10. */
  11. /*
  12. * SBC8641D board configuration file
  13. *
  14. * Make sure you change the MAC address and other network params first,
  15. * search for CONFIG_SERVERIP, etc in this file.
  16. */
  17. #ifndef __CONFIG_H
  18. #define __CONFIG_H
  19. /* High Level Configuration Options */
  20. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  21. #ifdef RUN_DIAG
  22. #define CONFIG_SYS_DIAG_ADDR 0xff800000
  23. #endif
  24. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  25. /*
  26. * virtual address to be used for temporary mappings. There
  27. * should be 128k free at this VA.
  28. */
  29. #define CONFIG_SYS_SCRATCH_VA 0xe8000000
  30. #define CONFIG_SYS_SRIO
  31. #define CONFIG_SRIO1 /* SRIO port 1 */
  32. #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
  33. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
  34. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  35. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  36. #define CONFIG_ENV_OVERWRITE
  37. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  38. #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
  39. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  40. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  41. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  42. #define CACHE_LINE_INTERLEAVING 0x20000000
  43. #define PAGE_INTERLEAVING 0x21000000
  44. #define BANK_INTERLEAVING 0x22000000
  45. #define SUPER_BANK_INTERLEAVING 0x23000000
  46. #define CONFIG_ALTIVEC 1
  47. /*
  48. * L2CR setup -- make sure this is right for your board!
  49. */
  50. #define CONFIG_SYS_L2
  51. #define L2_INIT 0
  52. #define L2_ENABLE (L2CR_L2E)
  53. #ifndef CONFIG_SYS_CLK_FREQ
  54. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  55. #endif
  56. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  57. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  58. #define CONFIG_SYS_MEMTEST_END 0x00400000
  59. /*
  60. * Base addresses -- Note these are effective addresses where the
  61. * actual resources get mapped (not physical addresses)
  62. */
  63. #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
  64. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  65. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  66. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  67. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
  68. /*
  69. * DDR Setup
  70. */
  71. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
  72. #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
  73. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  74. #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
  75. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  76. #define CONFIG_VERY_BIG_RAM
  77. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  78. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  79. #if defined(CONFIG_SPD_EEPROM)
  80. /*
  81. * Determine DDR configuration from I2C interface.
  82. */
  83. #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
  84. #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
  85. #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
  86. #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
  87. #else
  88. /*
  89. * Manually set up DDR1 & DDR2 parameters
  90. */
  91. #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
  92. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  93. #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
  94. #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
  95. #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
  96. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
  97. #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
  98. #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
  99. #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
  100. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  101. #define CONFIG_SYS_DDR_TIMING_0 0x00220802
  102. #define CONFIG_SYS_DDR_TIMING_1 0x38377322
  103. #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
  104. #define CONFIG_SYS_DDR_CFG_1A 0x43008008
  105. #define CONFIG_SYS_DDR_CFG_2 0x24401000
  106. #define CONFIG_SYS_DDR_MODE_1 0x23c00542
  107. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  108. #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
  109. #define CONFIG_SYS_DDR_INTERVAL 0x05080100
  110. #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
  111. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  112. #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
  113. #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
  114. #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
  115. #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
  116. #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
  117. #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
  118. #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
  119. #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
  120. #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
  121. #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
  122. #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
  123. #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
  124. #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
  125. #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
  126. #define CONFIG_SYS_DDR2_CFG_2 0x24401000
  127. #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
  128. #define CONFIG_SYS_DDR2_MODE_2 0x00000000
  129. #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
  130. #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
  131. #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
  132. #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
  133. #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
  134. #endif
  135. /* #define CONFIG_ID_EEPROM 1
  136. #define ID_EEPROM_ADDR 0x57 */
  137. /*
  138. * The SBC8641D contains 16MB flash space at ff000000.
  139. */
  140. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  141. /* Flash */
  142. #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
  143. #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
  144. /* 64KB EEPROM */
  145. #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
  146. #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
  147. /* EPLD - User switches, board id, LEDs */
  148. #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
  149. #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
  150. /* Local bus SDRAM 128MB */
  151. #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
  152. #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
  153. #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
  154. #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
  155. /* Disk on Chip (DOC) 128MB */
  156. #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
  157. #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
  158. /* LCD */
  159. #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
  160. #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
  161. /* Control logic & misc peripherals */
  162. #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
  163. #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
  164. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  165. #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
  166. #undef CONFIG_SYS_FLASH_CHECKSUM
  167. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  168. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  169. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  170. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  171. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  172. #define CONFIG_SYS_FLASH_EMPTY_INFO
  173. #undef CONFIG_CLOCKS_IN_MHZ
  174. #define CONFIG_SYS_INIT_RAM_LOCK 1
  175. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  176. #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
  177. #else
  178. #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
  179. #endif
  180. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  181. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  182. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  183. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  184. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  185. /* Serial Port */
  186. #define CONFIG_SYS_NS16550_SERIAL
  187. #define CONFIG_SYS_NS16550_REG_SIZE 1
  188. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  189. #define CONFIG_SYS_BAUDRATE_TABLE \
  190. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  191. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  192. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  193. /*
  194. * I2C
  195. */
  196. #define CONFIG_SYS_I2C
  197. #define CONFIG_SYS_I2C_FSL
  198. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  199. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  200. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  201. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  202. /*
  203. * RapidIO MMU
  204. */
  205. #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
  206. #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
  207. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
  208. /*
  209. * General PCI
  210. * Addresses are mapped 1-1.
  211. */
  212. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  213. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  214. #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
  215. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  216. #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
  217. #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
  218. #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
  219. #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
  220. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  221. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
  222. #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
  223. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  224. #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
  225. #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
  226. #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
  227. #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
  228. #if defined(CONFIG_PCI)
  229. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  230. #undef CONFIG_EEPRO100
  231. #undef CONFIG_TULIP
  232. #if !defined(CONFIG_PCI_PNP)
  233. #define PCI_ENET0_IOADDR 0xe0000000
  234. #define PCI_ENET0_MEMADDR 0xe0000000
  235. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  236. #endif
  237. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  238. #ifdef CONFIG_SCSI_AHCI
  239. #define CONFIG_SATA_ULI5288
  240. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  241. #define CONFIG_SYS_SCSI_MAX_LUN 1
  242. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  243. #endif
  244. #endif /* CONFIG_PCI */
  245. #if defined(CONFIG_TSEC_ENET)
  246. #define CONFIG_TSEC1 1
  247. #define CONFIG_TSEC1_NAME "eTSEC1"
  248. #define CONFIG_TSEC2 1
  249. #define CONFIG_TSEC2_NAME "eTSEC2"
  250. #define CONFIG_TSEC3 1
  251. #define CONFIG_TSEC3_NAME "eTSEC3"
  252. #define CONFIG_TSEC4 1
  253. #define CONFIG_TSEC4_NAME "eTSEC4"
  254. #define TSEC1_PHY_ADDR 0x1F
  255. #define TSEC2_PHY_ADDR 0x00
  256. #define TSEC3_PHY_ADDR 0x01
  257. #define TSEC4_PHY_ADDR 0x02
  258. #define TSEC1_PHYIDX 0
  259. #define TSEC2_PHYIDX 0
  260. #define TSEC3_PHYIDX 0
  261. #define TSEC4_PHYIDX 0
  262. #define TSEC1_FLAGS TSEC_GIGABIT
  263. #define TSEC2_FLAGS TSEC_GIGABIT
  264. #define TSEC3_FLAGS TSEC_GIGABIT
  265. #define TSEC4_FLAGS TSEC_GIGABIT
  266. #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
  267. #define CONFIG_ETHPRIME "eTSEC1"
  268. #endif /* CONFIG_TSEC_ENET */
  269. /*
  270. * BAT0 2G Cacheable, non-guarded
  271. * 0x0000_0000 2G DDR
  272. */
  273. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  274. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  275. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
  276. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  277. /*
  278. * BAT1 1G Cache-inhibited, guarded
  279. * 0x8000_0000 512M PCI-Express 1 Memory
  280. * 0xa000_0000 512M PCI-Express 2 Memory
  281. * Changed it for operating from 0xd0000000
  282. */
  283. #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
  284. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  285. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
  286. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  287. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  288. /*
  289. * BAT2 512M Cache-inhibited, guarded
  290. * 0xc000_0000 512M RapidIO Memory
  291. */
  292. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
  293. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  294. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
  295. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  296. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  297. /*
  298. * BAT3 4M Cache-inhibited, guarded
  299. * 0xf800_0000 4M CCSR
  300. */
  301. #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
  302. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  303. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
  304. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
  305. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  306. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  307. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  308. | BATL_PP_RW | BATL_CACHEINHIBIT \
  309. | BATL_GUARDEDSTORAGE)
  310. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  311. | BATU_BL_1M | BATU_VS | BATU_VP)
  312. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  313. | BATL_PP_RW | BATL_CACHEINHIBIT)
  314. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  315. #endif
  316. /*
  317. * BAT4 32M Cache-inhibited, guarded
  318. * 0xe200_0000 16M PCI-Express 1 I/O
  319. * 0xe300_0000 16M PCI-Express 2 I/0
  320. * Note that this is at 0xe0000000
  321. */
  322. #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
  323. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  324. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
  325. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  326. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  327. /*
  328. * BAT5 128K Cacheable, non-guarded
  329. * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
  330. */
  331. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  332. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  333. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  334. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  335. /*
  336. * BAT6 32M Cache-inhibited, guarded
  337. * 0xfe00_0000 32M FLASH
  338. */
  339. #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
  340. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  341. #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
  342. #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
  343. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  344. /* Map the last 1M of flash where we're running from reset */
  345. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  346. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  347. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  348. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  349. | BATL_MEMCOHERENCE)
  350. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  351. #define CONFIG_SYS_DBAT7L 0x00000000
  352. #define CONFIG_SYS_DBAT7U 0x00000000
  353. #define CONFIG_SYS_IBAT7L 0x00000000
  354. #define CONFIG_SYS_IBAT7U 0x00000000
  355. /*
  356. * Environment
  357. */
  358. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  359. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  360. #undef CONFIG_WATCHDOG /* watchdog disabled */
  361. /*
  362. * Miscellaneous configurable options
  363. */
  364. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  365. /*
  366. * For booting Linux, the board info and command line data
  367. * have to be in the first 8 MB of memory, since this is
  368. * the maximum mapped by the Linux kernel during initialization.
  369. */
  370. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  371. /* Cache Configuration */
  372. #define CONFIG_SYS_DCACHE_SIZE 32768
  373. #define CONFIG_SYS_CACHELINE_SIZE 32
  374. #if defined(CONFIG_CMD_KGDB)
  375. #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  376. #endif
  377. #if defined(CONFIG_CMD_KGDB)
  378. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  379. #endif
  380. /*
  381. * Environment Configuration
  382. */
  383. #define CONFIG_HAS_ETH0 1
  384. #define CONFIG_HAS_ETH1 1
  385. #define CONFIG_HAS_ETH2 1
  386. #define CONFIG_HAS_ETH3 1
  387. #define CONFIG_IPADDR 192.168.0.50
  388. #define CONFIG_HOSTNAME "sbc8641d"
  389. #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
  390. #define CONFIG_BOOTFILE "uImage"
  391. #define CONFIG_SERVERIP 192.168.0.2
  392. #define CONFIG_GATEWAYIP 192.168.0.1
  393. #define CONFIG_NETMASK 255.255.255.0
  394. /* default location for tftp and bootm */
  395. #define CONFIG_LOADADDR 1000000
  396. #define CONFIG_EXTRA_ENV_SETTINGS \
  397. "netdev=eth0\0" \
  398. "consoledev=ttyS0\0" \
  399. "ramdiskaddr=2000000\0" \
  400. "ramdiskfile=uRamdisk\0" \
  401. "dtbaddr=400000\0" \
  402. "dtbfile=sbc8641d.dtb\0" \
  403. "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
  404. "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
  405. "maxcpus=1"
  406. #define CONFIG_NFSBOOTCOMMAND \
  407. "setenv bootargs root=/dev/nfs rw " \
  408. "nfsroot=$serverip:$rootpath " \
  409. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  410. "console=$consoledev,$baudrate $othbootargs;" \
  411. "tftp $loadaddr $bootfile;" \
  412. "tftp $dtbaddr $dtbfile;" \
  413. "bootm $loadaddr - $dtbaddr"
  414. #define CONFIG_RAMBOOTCOMMAND \
  415. "setenv bootargs root=/dev/ram rw " \
  416. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  417. "console=$consoledev,$baudrate $othbootargs;" \
  418. "tftp $ramdiskaddr $ramdiskfile;" \
  419. "tftp $loadaddr $bootfile;" \
  420. "tftp $dtbaddr $dtbfile;" \
  421. "bootm $loadaddr $ramdiskaddr $dtbaddr"
  422. #define CONFIG_FLASHBOOTCOMMAND \
  423. "setenv bootargs root=/dev/ram rw " \
  424. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  425. "console=$consoledev,$baudrate $othbootargs;" \
  426. "bootm ffd00000 ffb00000 ffa00000"
  427. #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
  428. #endif /* __CONFIG_H */