sbc8548.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007,2009 Wind River Systems <www.windriver.com>
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. * Copyright 2004, 2007 Freescale Semiconductor.
  6. */
  7. /*
  8. * sbc8548 board configuration file
  9. * Please refer to doc/README.sbc8548 for more info.
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * Top level Makefile configuration choices
  15. */
  16. #ifdef CONFIG_PCI
  17. #define CONFIG_PCI_INDIRECT_BRIDGE
  18. #define CONFIG_PCI1
  19. #endif
  20. #ifdef CONFIG_66
  21. #define CONFIG_SYS_CLK_DIV 1
  22. #endif
  23. #ifdef CONFIG_33
  24. #define CONFIG_SYS_CLK_DIV 2
  25. #endif
  26. #ifdef CONFIG_PCIE
  27. #define CONFIG_PCIE1
  28. #endif
  29. /*
  30. * High Level Configuration Options
  31. */
  32. /*
  33. * If you want to boot from the SODIMM flash, instead of the soldered
  34. * on flash, set this, and change JP12, SW2:8 accordingly.
  35. */
  36. #undef CONFIG_SYS_ALT_BOOT
  37. #undef CONFIG_RIO
  38. #ifdef CONFIG_PCI
  39. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  40. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  41. #endif
  42. #define CONFIG_ENV_OVERWRITE
  43. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  44. /*
  45. * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  46. */
  47. #ifndef CONFIG_SYS_CLK_DIV
  48. #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
  49. #endif
  50. #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
  51. /*
  52. * These can be toggled for performance analysis, otherwise use default.
  53. */
  54. #define CONFIG_L2_CACHE /* toggle L2 cache */
  55. #define CONFIG_BTB /* toggle branch predition */
  56. /*
  57. * Only possible on E500 Version 2 or newer cores.
  58. */
  59. #define CONFIG_ENABLE_36BIT_PHYS 1
  60. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  61. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  62. #define CONFIG_SYS_MEMTEST_END 0x00400000
  63. #define CONFIG_SYS_CCSRBAR 0xe0000000
  64. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  65. /* DDR Setup */
  66. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  67. /*
  68. * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
  69. * to collide, meaning you couldn't reliably read either. So
  70. * physically remove the LBC PC100 SDRAM module from the board
  71. * before enabling the two SPD options below, or check that you
  72. * have the hardware fix on your board via "i2c probe" and looking
  73. * for a device at 0x53.
  74. */
  75. #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  76. #undef CONFIG_DDR_SPD
  77. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  78. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  79. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  80. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  81. #define CONFIG_VERY_BIG_RAM
  82. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  83. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  84. /*
  85. * The hardware fix for the I2C address collision puts the DDR
  86. * SPD at 0x53, but if we are running on an older board w/o the
  87. * fix, it will still be at 0x51. We check 0x53 1st.
  88. */
  89. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  90. #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
  91. /*
  92. * Make sure required options are set
  93. */
  94. #ifndef CONFIG_SPD_EEPROM
  95. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  96. #define CONFIG_SYS_DDR_CONTROL 0xc300c000
  97. #endif
  98. #undef CONFIG_CLOCKS_IN_MHZ
  99. /*
  100. * FLASH on the Local Bus
  101. * Two banks, one 8MB the other 64MB, using the CFI driver.
  102. * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
  103. * CS0 the 8MB boot flash, and CS6 the 64MB flash.
  104. *
  105. * Default:
  106. * ec00_0000 efff_ffff 64MB SODIMM
  107. * ff80_0000 ffff_ffff 8MB soldered flash
  108. *
  109. * Alternate:
  110. * ef80_0000 efff_ffff 8MB soldered flash
  111. * fc00_0000 ffff_ffff 64MB SODIMM
  112. *
  113. * BR0_8M:
  114. * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
  115. * Port Size = 8 bits = BRx[19:20] = 01
  116. * Use GPCM = BRx[24:26] = 000
  117. * Valid = BRx[31] = 1
  118. *
  119. * BR0_64M:
  120. * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
  121. * Port Size = 32 bits = BRx[19:20] = 11
  122. *
  123. * 0 4 8 12 16 20 24 28
  124. * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
  125. * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
  126. */
  127. #define CONFIG_SYS_BR0_8M 0xff800801
  128. #define CONFIG_SYS_BR0_64M 0xfc001801
  129. /*
  130. * BR6_8M:
  131. * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
  132. * Port Size = 8 bits = BRx[19:20] = 01
  133. * Use GPCM = BRx[24:26] = 000
  134. * Valid = BRx[31] = 1
  135. * BR6_64M:
  136. * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
  137. * Port Size = 32 bits = BRx[19:20] = 11
  138. *
  139. * 0 4 8 12 16 20 24 28
  140. * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
  141. * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
  142. */
  143. #define CONFIG_SYS_BR6_8M 0xef800801
  144. #define CONFIG_SYS_BR6_64M 0xec001801
  145. /*
  146. * OR0_8M:
  147. * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
  148. * XAM = OR0[17:18] = 11
  149. * CSNT = OR0[20] = 1
  150. * ACS = half cycle delay = OR0[21:22] = 11
  151. * SCY = 6 = OR0[24:27] = 0110
  152. * TRLX = use relaxed timing = OR0[29] = 1
  153. * EAD = use external address latch delay = OR0[31] = 1
  154. *
  155. * OR0_64M:
  156. * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
  157. *
  158. *
  159. * 0 4 8 12 16 20 24 28
  160. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
  161. * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
  162. */
  163. #define CONFIG_SYS_OR0_8M 0xff806e65
  164. #define CONFIG_SYS_OR0_64M 0xfc006e65
  165. /*
  166. * OR6_8M:
  167. * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
  168. * XAM = OR6[17:18] = 11
  169. * CSNT = OR6[20] = 1
  170. * ACS = half cycle delay = OR6[21:22] = 11
  171. * SCY = 6 = OR6[24:27] = 0110
  172. * TRLX = use relaxed timing = OR6[29] = 1
  173. * EAD = use external address latch delay = OR6[31] = 1
  174. *
  175. * OR6_64M:
  176. * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
  177. *
  178. * 0 4 8 12 16 20 24 28
  179. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
  180. * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
  181. */
  182. #define CONFIG_SYS_OR6_8M 0xff806e65
  183. #define CONFIG_SYS_OR6_64M 0xfc006e65
  184. #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
  185. #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
  186. #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
  187. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
  188. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
  189. #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
  190. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
  191. #else /* JP12 in alternate position */
  192. #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
  193. #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
  194. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
  195. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
  196. #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
  197. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
  198. #endif
  199. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
  200. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
  201. CONFIG_SYS_ALT_FLASH}
  202. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  203. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
  204. #undef CONFIG_SYS_FLASH_CHECKSUM
  205. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  206. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  207. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  208. #define CONFIG_SYS_FLASH_EMPTY_INFO
  209. /* CS5 = Local bus peripherals controlled by the EPLD */
  210. #define CONFIG_SYS_BR5_PRELIM 0xf8000801
  211. #define CONFIG_SYS_OR5_PRELIM 0xff006e65
  212. #define CONFIG_SYS_EPLD_BASE 0xf8000000
  213. #define CONFIG_SYS_LED_DISP_BASE 0xf8000000
  214. #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
  215. #define CONFIG_SYS_BD_REV 0xf8300000
  216. #define CONFIG_SYS_EEPROM_BASE 0xf8b00000
  217. /*
  218. * SDRAM on the Local Bus (CS3 and CS4)
  219. * Note that most boards have a hardware errata where both the
  220. * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
  221. * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
  222. * A hardware workaround is also available, see README.sbc8548 file.
  223. */
  224. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  225. #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
  226. /*
  227. * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
  228. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  229. *
  230. * For BR3, need:
  231. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  232. * port-size = 32-bits = BR2[19:20] = 11
  233. * no parity checking = BR2[21:22] = 00
  234. * SDRAM for MSEL = BR2[24:26] = 011
  235. * Valid = BR[31] = 1
  236. *
  237. * 0 4 8 12 16 20 24 28
  238. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  239. *
  240. */
  241. #define CONFIG_SYS_BR3_PRELIM 0xf0001861
  242. /*
  243. * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  244. *
  245. * For OR3, need:
  246. * 64MB mask for AM, OR3[0:7] = 1111 1100
  247. * XAM, OR3[17:18] = 11
  248. * 10 columns OR3[19-21] = 011
  249. * 12 rows OR3[23-25] = 011
  250. * EAD set for extra time OR[31] = 0
  251. *
  252. * 0 4 8 12 16 20 24 28
  253. * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
  254. */
  255. #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
  256. /*
  257. * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
  258. * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
  259. *
  260. * For BR4, need:
  261. * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
  262. * port-size = 32-bits = BR2[19:20] = 11
  263. * no parity checking = BR2[21:22] = 00
  264. * SDRAM for MSEL = BR2[24:26] = 011
  265. * Valid = BR[31] = 1
  266. *
  267. * 0 4 8 12 16 20 24 28
  268. * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
  269. *
  270. */
  271. #define CONFIG_SYS_BR4_PRELIM 0xf4001861
  272. /*
  273. * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  274. *
  275. * For OR4, need:
  276. * 64MB mask for AM, OR3[0:7] = 1111 1100
  277. * XAM, OR3[17:18] = 11
  278. * 10 columns OR3[19-21] = 011
  279. * 12 rows OR3[23-25] = 011
  280. * EAD set for extra time OR[31] = 0
  281. *
  282. * 0 4 8 12 16 20 24 28
  283. * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
  284. */
  285. #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
  286. #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
  287. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  288. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  289. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  290. /*
  291. * Common settings for all Local Bus SDRAM commands.
  292. */
  293. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  294. | LSDMR_BSMA1516 \
  295. | LSDMR_PRETOACT3 \
  296. | LSDMR_ACTTORW3 \
  297. | LSDMR_BUFCMD \
  298. | LSDMR_BL8 \
  299. | LSDMR_WRC2 \
  300. | LSDMR_CL3 \
  301. )
  302. #define CONFIG_SYS_LBC_LSDMR_PCHALL \
  303. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  304. #define CONFIG_SYS_LBC_LSDMR_ARFRSH \
  305. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  306. #define CONFIG_SYS_LBC_LSDMR_MRW \
  307. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  308. #define CONFIG_SYS_LBC_LSDMR_RFEN \
  309. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
  310. #define CONFIG_SYS_INIT_RAM_LOCK 1
  311. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  312. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  313. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
  314. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  315. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  316. /*
  317. * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
  318. * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
  319. * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
  320. * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
  321. * thing for MONITOR_LEN in both cases.
  322. */
  323. #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
  324. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  325. /* Serial Port */
  326. #define CONFIG_SYS_NS16550_SERIAL
  327. #define CONFIG_SYS_NS16550_REG_SIZE 1
  328. #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
  329. #define CONFIG_SYS_BAUDRATE_TABLE \
  330. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  331. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  332. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  333. /*
  334. * I2C
  335. */
  336. #define CONFIG_SYS_I2C
  337. #define CONFIG_SYS_I2C_FSL
  338. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  339. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  340. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  341. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  342. /*
  343. * General PCI
  344. * Memory space is mapped 1-1, but I/O space must start from 0.
  345. */
  346. #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
  347. #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
  348. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  349. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  350. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  351. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  352. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  353. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  354. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  355. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
  356. #ifdef CONFIG_PCIE1
  357. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  358. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  359. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  360. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  361. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  362. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  363. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  364. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  365. #endif
  366. #ifdef CONFIG_RIO
  367. /*
  368. * RapidIO MMU
  369. */
  370. #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
  371. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
  372. #endif
  373. #if defined(CONFIG_PCI)
  374. #undef CONFIG_EEPRO100
  375. #undef CONFIG_TULIP
  376. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  377. #endif /* CONFIG_PCI */
  378. #if defined(CONFIG_TSEC_ENET)
  379. #define CONFIG_TSEC1 1
  380. #define CONFIG_TSEC1_NAME "eTSEC0"
  381. #define CONFIG_TSEC2 1
  382. #define CONFIG_TSEC2_NAME "eTSEC1"
  383. #undef CONFIG_MPC85XX_FEC
  384. #define TSEC1_PHY_ADDR 0x19
  385. #define TSEC2_PHY_ADDR 0x1a
  386. #define TSEC1_PHYIDX 0
  387. #define TSEC2_PHYIDX 0
  388. #define TSEC1_FLAGS TSEC_GIGABIT
  389. #define TSEC2_FLAGS TSEC_GIGABIT
  390. /* Options are: eTSEC[0-3] */
  391. #define CONFIG_ETHPRIME "eTSEC0"
  392. #endif /* CONFIG_TSEC_ENET */
  393. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  394. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  395. /*
  396. * BOOTP options
  397. */
  398. #define CONFIG_BOOTP_BOOTFILESIZE
  399. #undef CONFIG_WATCHDOG /* watchdog disabled */
  400. /*
  401. * Miscellaneous configurable options
  402. */
  403. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  404. /*
  405. * For booting Linux, the board info and command line data
  406. * have to be in the first 8 MB of memory, since this is
  407. * the maximum mapped by the Linux kernel during initialization.
  408. */
  409. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  410. #if defined(CONFIG_CMD_KGDB)
  411. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  412. #endif
  413. /*
  414. * Environment Configuration
  415. */
  416. #if defined(CONFIG_TSEC_ENET)
  417. #define CONFIG_HAS_ETH0
  418. #define CONFIG_HAS_ETH1
  419. #endif
  420. #define CONFIG_IPADDR 192.168.0.55
  421. #define CONFIG_HOSTNAME "sbc8548"
  422. #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
  423. #define CONFIG_BOOTFILE "/uImage"
  424. #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
  425. #define CONFIG_SERVERIP 192.168.0.2
  426. #define CONFIG_GATEWAYIP 192.168.0.1
  427. #define CONFIG_NETMASK 255.255.255.0
  428. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  429. #define CONFIG_EXTRA_ENV_SETTINGS \
  430. "netdev=eth0\0" \
  431. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  432. "tftpflash=tftpboot $loadaddr $uboot; " \
  433. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  434. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  435. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  436. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  437. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  438. "consoledev=ttyS0\0" \
  439. "ramdiskaddr=2000000\0" \
  440. "ramdiskfile=uRamdisk\0" \
  441. "fdtaddr=1e00000\0" \
  442. "fdtfile=sbc8548.dtb\0"
  443. #define CONFIG_NFSBOOTCOMMAND \
  444. "setenv bootargs root=/dev/nfs rw " \
  445. "nfsroot=$serverip:$rootpath " \
  446. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  447. "console=$consoledev,$baudrate $othbootargs;" \
  448. "tftp $loadaddr $bootfile;" \
  449. "tftp $fdtaddr $fdtfile;" \
  450. "bootm $loadaddr - $fdtaddr"
  451. #define CONFIG_RAMBOOTCOMMAND \
  452. "setenv bootargs root=/dev/ram rw " \
  453. "console=$consoledev,$baudrate $othbootargs;" \
  454. "tftp $ramdiskaddr $ramdiskfile;" \
  455. "tftp $loadaddr $bootfile;" \
  456. "tftp $fdtaddr $fdtfile;" \
  457. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  458. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  459. #endif /* __CONFIG_H */