sbc8349.h 9.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * WindRiver SBC8349 U-Boot configuration file.
  4. * Copyright (c) 2006, 2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on the MPC8349EMDS config.
  8. */
  9. /*
  10. * sbc8349 board configuration file.
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_E300 1 /* E300 Family */
  18. /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  19. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  20. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  21. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  22. #define CONFIG_SYS_MEMTEST_END 0x00100000
  23. /*
  24. * DDR Setup
  25. */
  26. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  27. #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  28. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  29. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
  30. /*
  31. * 32-bit data path mode.
  32. *
  33. * Please note that using this mode for devices with the real density of 64-bit
  34. * effectively reduces the amount of available memory due to the effect of
  35. * wrapping around while translating address to row/columns, for example in the
  36. * 256MB module the upper 128MB get aliased with contents of the lower
  37. * 128MB); normally this define should be used for devices with real 32-bit
  38. * data path.
  39. */
  40. #undef CONFIG_DDR_32BIT
  41. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  42. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
  43. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  44. #define CONFIG_DDR_2T_TIMING
  45. #if defined(CONFIG_SPD_EEPROM)
  46. /*
  47. * Determine DDR configuration from I2C interface.
  48. */
  49. #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
  50. #else
  51. /*
  52. * Manually set up DDR parameters
  53. * NB: manual DDR setup untested on sbc834x
  54. */
  55. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  56. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  57. | CSCONFIG_ROW_BIT_13 \
  58. | CSCONFIG_COL_BIT_10)
  59. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  60. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  61. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  62. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  63. #if defined(CONFIG_DDR_32BIT)
  64. /* set burst length to 8 for 32-bit data path */
  65. /* DLL,normal,seq,4/2.5, 8 burst len */
  66. #define CONFIG_SYS_DDR_MODE 0x00000023
  67. #else
  68. /* the default burst length is 4 - for 64-bit data path */
  69. /* DLL,normal,seq,4/2.5, 4 burst len */
  70. #define CONFIG_SYS_DDR_MODE 0x00000022
  71. #endif
  72. #endif
  73. /*
  74. * SDRAM on the Local Bus
  75. */
  76. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  77. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  78. /*
  79. * FLASH on the Local Bus
  80. */
  81. #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
  82. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  83. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  84. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  85. #undef CONFIG_SYS_FLASH_CHECKSUM
  86. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  87. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  88. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  89. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  90. #define CONFIG_SYS_RAMBOOT
  91. #else
  92. #undef CONFIG_SYS_RAMBOOT
  93. #endif
  94. #define CONFIG_SYS_INIT_RAM_LOCK 1
  95. /* Initial RAM address */
  96. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  97. /* Size of used area in RAM*/
  98. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  99. #define CONFIG_SYS_GBL_DATA_OFFSET \
  100. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  101. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  102. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  103. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  104. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  105. /*
  106. * Serial Port
  107. */
  108. #define CONFIG_SYS_NS16550_SERIAL
  109. #define CONFIG_SYS_NS16550_REG_SIZE 1
  110. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  111. #define CONFIG_SYS_BAUDRATE_TABLE \
  112. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  113. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  114. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  115. /* I2C */
  116. #define CONFIG_SYS_I2C
  117. #define CONFIG_SYS_I2C_FSL
  118. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  119. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  120. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  121. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  122. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  123. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  124. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
  125. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  126. /* TSEC */
  127. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  128. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  129. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  130. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  131. /*
  132. * General PCI
  133. * Addresses are mapped 1-1.
  134. */
  135. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  136. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  137. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  138. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  139. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  140. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  141. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  142. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  143. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  144. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  145. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  146. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  147. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  148. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  149. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  150. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  151. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  152. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  153. #if defined(CONFIG_PCI)
  154. #undef CONFIG_EEPRO100
  155. #undef CONFIG_TULIP
  156. #if !defined(CONFIG_PCI_PNP)
  157. #define PCI_ENET0_IOADDR 0xFIXME
  158. #define PCI_ENET0_MEMADDR 0xFIXME
  159. #define PCI_IDSEL_NUMBER 0xFIXME
  160. #endif
  161. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  162. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  163. #endif /* CONFIG_PCI */
  164. /*
  165. * TSEC configuration
  166. */
  167. #if defined(CONFIG_TSEC_ENET)
  168. #define CONFIG_TSEC1 1
  169. #define CONFIG_TSEC1_NAME "TSEC0"
  170. #define CONFIG_TSEC2 1
  171. #define CONFIG_TSEC2_NAME "TSEC1"
  172. #define CONFIG_PHY_BCM5421S 1
  173. #define TSEC1_PHY_ADDR 0x19
  174. #define TSEC2_PHY_ADDR 0x1a
  175. #define TSEC1_PHYIDX 0
  176. #define TSEC2_PHYIDX 0
  177. #define TSEC1_FLAGS TSEC_GIGABIT
  178. #define TSEC2_FLAGS TSEC_GIGABIT
  179. /* Options are: TSEC[0-1] */
  180. #define CONFIG_ETHPRIME "TSEC0"
  181. #endif /* CONFIG_TSEC_ENET */
  182. /*
  183. * Environment
  184. */
  185. #ifndef CONFIG_SYS_RAMBOOT
  186. /* Address and size of Redundant Environment Sector */
  187. #endif
  188. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  189. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  190. /*
  191. * BOOTP options
  192. */
  193. #define CONFIG_BOOTP_BOOTFILESIZE
  194. /*
  195. * Command line configuration.
  196. */
  197. #undef CONFIG_WATCHDOG /* watchdog disabled */
  198. /*
  199. * Miscellaneous configurable options
  200. */
  201. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  202. /*
  203. * For booting Linux, the board info and command line data
  204. * have to be in the first 256 MB of memory, since this is
  205. * the maximum mapped by the Linux kernel during initialization.
  206. */
  207. /* Initial Memory map for Linux*/
  208. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  209. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  210. /* System IO Config */
  211. #define CONFIG_SYS_SICRH 0
  212. #define CONFIG_SYS_SICRL SICRL_LDP_A
  213. #ifdef CONFIG_PCI
  214. #define CONFIG_PCI_INDIRECT_BRIDGE
  215. #endif
  216. #if defined(CONFIG_CMD_KGDB)
  217. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  218. #endif
  219. /*
  220. * Environment Configuration
  221. */
  222. #define CONFIG_ENV_OVERWRITE
  223. #if defined(CONFIG_TSEC_ENET)
  224. #define CONFIG_HAS_ETH0
  225. #define CONFIG_HAS_ETH1
  226. #endif
  227. #define CONFIG_HOSTNAME "SBC8349"
  228. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  229. #define CONFIG_BOOTFILE "uImage"
  230. /* default location for tftp and bootm */
  231. #define CONFIG_LOADADDR 800000
  232. #define CONFIG_EXTRA_ENV_SETTINGS \
  233. "netdev=eth0\0" \
  234. "hostname=sbc8349\0" \
  235. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  236. "nfsroot=${serverip}:${rootpath}\0" \
  237. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  238. "addip=setenv bootargs ${bootargs} " \
  239. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  240. ":${hostname}:${netdev}:off panic=1\0" \
  241. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  242. "flash_nfs=run nfsargs addip addtty;" \
  243. "bootm ${kernel_addr}\0" \
  244. "flash_self=run ramargs addip addtty;" \
  245. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  246. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  247. "bootm\0" \
  248. "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
  249. "update=protect off ff800000 ff83ffff; " \
  250. "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
  251. "upd=run load update\0" \
  252. "fdtaddr=780000\0" \
  253. "fdtfile=sbc8349.dtb\0" \
  254. ""
  255. #define CONFIG_NFSBOOTCOMMAND \
  256. "setenv bootargs root=/dev/nfs rw " \
  257. "nfsroot=$serverip:$rootpath " \
  258. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  259. "$netdev:off " \
  260. "console=$consoledev,$baudrate $othbootargs;" \
  261. "tftp $loadaddr $bootfile;" \
  262. "tftp $fdtaddr $fdtfile;" \
  263. "bootm $loadaddr - $fdtaddr"
  264. #define CONFIG_RAMBOOTCOMMAND \
  265. "setenv bootargs root=/dev/ram rw " \
  266. "console=$consoledev,$baudrate $othbootargs;" \
  267. "tftp $ramdiskaddr $ramdiskfile;" \
  268. "tftp $loadaddr $bootfile;" \
  269. "tftp $fdtaddr $fdtfile;" \
  270. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  271. #define CONFIG_BOOTCOMMAND "run flash_self"
  272. #endif /* __CONFIG_H */