rk3308_common.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef __CONFIG_RK3308_COMMON_H
  6. #define __CONFIG_RK3308_COMMON_H
  7. #include "rockchip-common.h"
  8. #define CONFIG_SYS_CBSIZE 1024
  9. #define CONFIG_SKIP_LOWLEVEL_INIT
  10. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  11. #define CONFIG_SYS_NAND_ONFI_DETECTION
  12. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  13. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  14. #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
  15. #define CONFIG_SPL_MAX_SIZE 0x20000
  16. #define CONFIG_SPL_BSS_START_ADDR 0x00400000
  17. #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
  18. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
  19. #define CONFIG_SYS_NS16550_MEM32
  20. #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
  21. #define CONFIG_IRAM_BASE 0xfff80000
  22. #define CONFIG_SYS_INIT_SP_ADDR 0x00800000
  23. #define CONFIG_SYS_LOAD_ADDR 0x00C00800
  24. #define CONFIG_SPL_STACK 0x00400000
  25. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
  26. #define COUNTER_FREQUENCY 24000000
  27. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
  28. #define CONFIG_SYS_SDRAM_BASE 0
  29. #define SDRAM_MAX_SIZE 0xff000000
  30. #define SDRAM_BANK_SIZE (2UL << 30)
  31. #ifndef CONFIG_SPL_BUILD
  32. #define ENV_MEM_LAYOUT_SETTINGS \
  33. "scriptaddr=0x00500000\0" \
  34. "pxefile_addr_r=0x00600000\0" \
  35. "fdt_addr_r=0x02800000\0" \
  36. "kernel_addr_r=0x00680000\0" \
  37. "ramdisk_addr_r=0x04000000\0"
  38. #include <config_distro_bootcmd.h>
  39. #define CONFIG_EXTRA_ENV_SETTINGS \
  40. ENV_MEM_LAYOUT_SETTINGS \
  41. "partitions=" PARTS_DEFAULT \
  42. ROCKCHIP_DEVICE_SETTINGS \
  43. BOOTENV
  44. #endif
  45. #endif