pm9263.h 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Ilko Iliev <www.ronetix.at>
  7. *
  8. * Configuation settings for the RONETIX PM9263 board.
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * SoC must be defined first, before hardware.h is included.
  14. * In this case SoC is defined in boards.cfg.
  15. */
  16. #include <asm/hardware.h>
  17. /* ARM asynchronous clock */
  18. #define MASTER_PLL_DIV 6
  19. #define MASTER_PLL_MUL 65
  20. #define MAIN_PLL_DIV 2 /* 2 or 4 */
  21. #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
  22. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
  23. #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
  24. #define CONFIG_MACH_TYPE MACH_TYPE_PM9263
  25. /* clocks */
  26. #define CONFIG_SYS_MOR_VAL \
  27. (AT91_PMC_MOR_MOSCEN | \
  28. (255 << 8)) /* Main Oscillator Start-up Time */
  29. #define CONFIG_SYS_PLLAR_VAL \
  30. (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  31. AT91_PMC_PLLXR_OUT(3) | \
  32. AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
  33. (2 << 28) | /* PLL Clock Frequency Range */ \
  34. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  35. #if (MAIN_PLL_DIV == 2)
  36. /* PCK/2 = MCK Master Clock from PLLA */
  37. #define CONFIG_SYS_MCKR1_VAL \
  38. (AT91_PMC_MCKR_CSS_SLOW | \
  39. AT91_PMC_MCKR_PRES_1 | \
  40. AT91_PMC_MCKR_MDIV_2)
  41. /* PCK/2 = MCK Master Clock from PLLA */
  42. #define CONFIG_SYS_MCKR2_VAL \
  43. (AT91_PMC_MCKR_CSS_PLLA | \
  44. AT91_PMC_MCKR_PRES_1 | \
  45. AT91_PMC_MCKR_MDIV_2)
  46. #else
  47. /* PCK/4 = MCK Master Clock from PLLA */
  48. #define CONFIG_SYS_MCKR1_VAL \
  49. (AT91_PMC_MCKR_CSS_SLOW | \
  50. AT91_PMC_MCKR_PRES_1 | \
  51. AT91_PMC_MCKR_MDIV_4)
  52. /* PCK/4 = MCK Master Clock from PLLA */
  53. #define CONFIG_SYS_MCKR2_VAL \
  54. (AT91_PMC_MCKR_CSS_PLLA | \
  55. AT91_PMC_MCKR_PRES_1 | \
  56. AT91_PMC_MCKR_MDIV_4)
  57. #endif
  58. /* define PDC[31:16] as DATA[31:16] */
  59. #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
  60. /* no pull-up for D[31:16] */
  61. #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
  62. /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  63. #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
  64. (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
  65. AT91_MATRIX_CSA_EBI_CS1A)
  66. /* SDRAM */
  67. /* SDRAMC_MR Mode register */
  68. #define CONFIG_SYS_SDRC_MR_VAL1 0
  69. /* SDRAMC_TR - Refresh Timer register */
  70. #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
  71. /* SDRAMC_CR - Configuration register*/
  72. #define CONFIG_SYS_SDRC_CR_VAL \
  73. (AT91_SDRAMC_NC_9 | \
  74. AT91_SDRAMC_NR_13 | \
  75. AT91_SDRAMC_NB_4 | \
  76. AT91_SDRAMC_CAS_2 | \
  77. AT91_SDRAMC_DBW_32 | \
  78. (2 << 8) | /* tWR - Write Recovery Delay */ \
  79. (7 << 12) | /* tRC - Row Cycle Delay */ \
  80. (2 << 16) | /* tRP - Row Precharge Delay */ \
  81. (2 << 20) | /* tRCD - Row to Column Delay */ \
  82. (5 << 24) | /* tRAS - Active to Precharge Delay */ \
  83. (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
  84. /* Memory Device Register -> SDRAM */
  85. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  86. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  87. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  88. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  89. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  90. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  91. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  92. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  93. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  94. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  95. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  96. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  97. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  98. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  99. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  100. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  101. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  102. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  103. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  104. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  105. (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
  106. AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
  107. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  108. (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
  109. AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
  110. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  111. (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
  112. #define CONFIG_SYS_SMC0_MODE0_VAL \
  113. (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
  114. AT91_SMC_MODE_DBW_16 | \
  115. AT91_SMC_MODE_TDF | \
  116. AT91_SMC_MODE_TDF_CYCLE(6))
  117. /* user reset enable */
  118. #define CONFIG_SYS_RSTC_RMR_VAL \
  119. (AT91_RSTC_KEY | \
  120. AT91_RSTC_CR_PROCRST | \
  121. AT91_RSTC_MR_ERSTL(1) | \
  122. AT91_RSTC_MR_ERSTL(2))
  123. /* Disable Watchdog */
  124. #define CONFIG_SYS_WDTC_WDMR_VAL \
  125. (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
  126. AT91_WDT_MR_WDV(0xfff) | \
  127. AT91_WDT_MR_WDDIS | \
  128. AT91_WDT_MR_WDD(0xfff))
  129. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  130. #define CONFIG_SETUP_MEMORY_TAGS 1
  131. #define CONFIG_INITRD_TAG 1
  132. #undef CONFIG_SKIP_LOWLEVEL_INIT
  133. #define CONFIG_USER_LOWLEVEL_INIT 1
  134. /*
  135. * Hardware drivers
  136. */
  137. /* LCD */
  138. #define LCD_BPP LCD_COLOR8
  139. #define CONFIG_LCD_LOGO 1
  140. #undef LCD_TEST_PATTERN
  141. #define CONFIG_LCD_INFO 1
  142. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  143. #define CONFIG_ATMEL_LCD 1
  144. #define CONFIG_ATMEL_LCD_BGR555 1
  145. #define CONFIG_LCD_IN_PSRAM 1
  146. /*
  147. * BOOTP options
  148. */
  149. #define CONFIG_BOOTP_BOOTFILESIZE 1
  150. /* SDRAM */
  151. #define PHYS_SDRAM 0x20000000
  152. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  153. /* NOR flash, if populated */
  154. #define PHYS_FLASH_1 0x10000000
  155. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  156. #define CONFIG_SYS_MAX_FLASH_SECT 256
  157. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  158. /* NAND flash */
  159. #ifdef CONFIG_CMD_NAND
  160. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  161. #define CONFIG_SYS_NAND_BASE 0x40000000
  162. #define CONFIG_SYS_NAND_DBW_8 1
  163. /* our ALE is AD21 */
  164. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  165. /* our CLE is AD22 */
  166. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  167. #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
  168. #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
  169. #endif
  170. #define CONFIG_JFFS2_CMDLINE 1
  171. #define CONFIG_JFFS2_NAND 1
  172. #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
  173. #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
  174. #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
  175. /* PSRAM */
  176. #define PHYS_PSRAM 0x70000000
  177. #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
  178. /* Slave EBI1, PSRAM connected */
  179. #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
  180. AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
  181. AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
  182. AT91_MATRIX_SCFG_SLOT_CYCLE(255))
  183. /* Ethernet */
  184. #define CONFIG_MACB 1
  185. #define CONFIG_RMII 1
  186. #define CONFIG_NET_RETRY_COUNT 20
  187. #define CONFIG_RESET_PHY_R 1
  188. /* USB */
  189. #define CONFIG_USB_ATMEL
  190. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  191. #define CONFIG_USB_OHCI_NEW 1
  192. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  193. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
  194. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
  195. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  196. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  197. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  198. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  199. #define CONFIG_SYS_USE_FLASH 1
  200. #undef CONFIG_SYS_USE_DATAFLASH
  201. #undef CONFIG_SYS_USE_NANDFLASH
  202. #ifdef CONFIG_SYS_USE_DATAFLASH
  203. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  204. #define CONFIG_BOOTCOMMAND "sf probe 0; " \
  205. "sf read 0x22000000 0x84000 0x294000; " \
  206. "bootm 0x22000000"
  207. #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
  208. /* bootstrap + u-boot + env + linux in nandflash */
  209. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  210. #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
  211. #define CONFIG_ENV_OVERWRITE 1
  212. /* JFFS Partition offset set */
  213. #define CONFIG_SYS_JFFS2_FIRST_BANK 0
  214. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  215. /* 512k reserved for u-boot */
  216. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
  217. #define CONFIG_BOOTCOMMAND "run flashboot"
  218. #define CONFIG_ROOTPATH "/ronetix/rootfs"
  219. #define CONFIG_CON_ROT "fbcon=rotate:3 "
  220. #define CONFIG_EXTRA_ENV_SETTINGS \
  221. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  222. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  223. "partition=nand0,0\0" \
  224. "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  225. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  226. CONFIG_CON_ROT \
  227. "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
  228. "addip=setenv bootargs $(bootargs) " \
  229. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
  230. ":$(hostname):eth0:off\0" \
  231. "ramboot=tftpboot 0x22000000 vmImage;" \
  232. "run ramargs;run addip;bootm 22000000\0" \
  233. "nfsboot=tftpboot 0x22000000 vmImage;" \
  234. "run nfsargs;run addip;bootm 22000000\0" \
  235. "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
  236. ""
  237. #else
  238. #error "Undefined memory device"
  239. #endif
  240. /*
  241. * Size of malloc() pool
  242. */
  243. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  244. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  245. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
  246. GENERATED_GBL_DATA_SIZE)
  247. #endif