pm9261.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Ilko Iliev <www.ronetix.at>
  7. *
  8. * Configuation settings for the RONETIX PM9261 board.
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * SoC must be defined first, before hardware.h is included.
  14. * In this case SoC is defined in boards.cfg.
  15. */
  16. #include <asm/hardware.h>
  17. /* ARM asynchronous clock */
  18. #define MASTER_PLL_DIV 15
  19. #define MASTER_PLL_MUL 162
  20. #define MAIN_PLL_DIV 2
  21. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
  22. #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
  23. #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
  24. #define CONFIG_MACH_TYPE MACH_TYPE_PM9261
  25. /* clocks */
  26. /* CKGR_MOR - enable main osc. */
  27. #define CONFIG_SYS_MOR_VAL \
  28. (AT91_PMC_MOR_MOSCEN | \
  29. (255 << 8)) /* Main Oscillator Start-up Time */
  30. #define CONFIG_SYS_PLLAR_VAL \
  31. (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  32. AT91_PMC_PLLXR_OUT(3) | \
  33. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  34. /* PCK/2 = MCK Master Clock from PLLA */
  35. #define CONFIG_SYS_MCKR1_VAL \
  36. (AT91_PMC_MCKR_CSS_SLOW | \
  37. AT91_PMC_MCKR_PRES_1 | \
  38. AT91_PMC_MCKR_MDIV_2)
  39. /* PCK/2 = MCK Master Clock from PLLA */
  40. #define CONFIG_SYS_MCKR2_VAL \
  41. (AT91_PMC_MCKR_CSS_PLLA | \
  42. AT91_PMC_MCKR_PRES_1 | \
  43. AT91_PMC_MCKR_MDIV_2)
  44. /* define PDC[31:16] as DATA[31:16] */
  45. #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
  46. /* no pull-up for D[31:16] */
  47. #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
  48. /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  49. #define CONFIG_SYS_MATRIX_EBICSA_VAL \
  50. (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
  51. /* SDRAM */
  52. /* SDRAMC_MR Mode register */
  53. #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
  54. /* SDRAMC_TR - Refresh Timer register */
  55. #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
  56. /* SDRAMC_CR - Configuration register*/
  57. #define CONFIG_SYS_SDRC_CR_VAL \
  58. (AT91_SDRAMC_NC_9 | \
  59. AT91_SDRAMC_NR_13 | \
  60. AT91_SDRAMC_NB_4 | \
  61. AT91_SDRAMC_CAS_3 | \
  62. AT91_SDRAMC_DBW_32 | \
  63. (1 << 8) | /* Write Recovery Delay */ \
  64. (7 << 12) | /* Row Cycle Delay */ \
  65. (3 << 16) | /* Row Precharge Delay */ \
  66. (2 << 20) | /* Row to Column Delay */ \
  67. (5 << 24) | /* Active to Precharge Delay */ \
  68. (1 << 28)) /* Exit Self Refresh to Active Delay */
  69. /* Memory Device Register -> SDRAM */
  70. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  71. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  72. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  73. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  74. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  75. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  76. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  77. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  78. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  79. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  80. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  81. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  82. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  83. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  84. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  85. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  86. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  87. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  88. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  89. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  90. (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
  91. AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
  92. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  93. (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
  94. AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
  95. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  96. (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
  97. #define CONFIG_SYS_SMC0_MODE0_VAL \
  98. (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
  99. AT91_SMC_MODE_DBW_16 | \
  100. AT91_SMC_MODE_TDF | \
  101. AT91_SMC_MODE_TDF_CYCLE(6))
  102. /* user reset enable */
  103. #define CONFIG_SYS_RSTC_RMR_VAL \
  104. (AT91_RSTC_KEY | \
  105. AT91_RSTC_CR_PROCRST | \
  106. AT91_RSTC_MR_ERSTL(1) | \
  107. AT91_RSTC_MR_ERSTL(2))
  108. /* Disable Watchdog */
  109. #define CONFIG_SYS_WDTC_WDMR_VAL \
  110. (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
  111. AT91_WDT_MR_WDV(0xfff) | \
  112. AT91_WDT_MR_WDDIS | \
  113. AT91_WDT_MR_WDD(0xfff))
  114. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  115. #define CONFIG_SETUP_MEMORY_TAGS 1
  116. #define CONFIG_INITRD_TAG 1
  117. #undef CONFIG_SKIP_LOWLEVEL_INIT
  118. /*
  119. * Hardware drivers
  120. */
  121. /* LCD */
  122. #define LCD_BPP LCD_COLOR8
  123. #define CONFIG_LCD_LOGO 1
  124. #undef LCD_TEST_PATTERN
  125. #define CONFIG_LCD_INFO 1
  126. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  127. #define CONFIG_ATMEL_LCD 1
  128. #define CONFIG_ATMEL_LCD_BGR555 1
  129. /*
  130. * BOOTP options
  131. */
  132. #define CONFIG_BOOTP_BOOTFILESIZE 1
  133. /* SDRAM */
  134. #define PHYS_SDRAM 0x20000000
  135. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  136. /* NAND flash */
  137. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  138. #define CONFIG_SYS_NAND_BASE 0x40000000
  139. #define CONFIG_SYS_NAND_DBW_8 1
  140. /* our ALE is AD22 */
  141. #define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
  142. /* our CLE is AD21 */
  143. #define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
  144. #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
  145. #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
  146. /* NOR flash */
  147. #define PHYS_FLASH_1 0x10000000
  148. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  149. #define CONFIG_SYS_MAX_FLASH_SECT 256
  150. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  151. /* Ethernet */
  152. #define CONFIG_DRIVER_DM9000 1
  153. #define CONFIG_DM9000_BASE 0x30000000
  154. #define DM9000_IO CONFIG_DM9000_BASE
  155. #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  156. #define CONFIG_DM9000_USE_16BIT 1
  157. #define CONFIG_NET_RETRY_COUNT 20
  158. #define CONFIG_RESET_PHY_R 1
  159. /* USB */
  160. #define CONFIG_USB_ATMEL
  161. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  162. #define CONFIG_USB_OHCI_NEW 1
  163. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  164. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
  165. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
  166. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  167. #define CONFIG_SYS_LOAD_ADDR 0x22000000
  168. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  169. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  170. #undef CONFIG_SYS_USE_DATAFLASH_CS0
  171. #undef CONFIG_SYS_USE_NANDFLASH
  172. #define CONFIG_SYS_USE_FLASH 1
  173. #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
  174. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  175. #define CONFIG_BOOTCOMMAND "sf probe 0; " \
  176. "sf read 0x22000000 0x84000 0x210000; " \
  177. "bootm 0x22000000"
  178. #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
  179. /* bootstrap + u-boot + env + linux in nandflash */
  180. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  181. #elif defined (CONFIG_SYS_USE_FLASH)
  182. #define CONFIG_ENV_OVERWRITE 1
  183. /* JFFS Partition offset set */
  184. #define CONFIG_SYS_JFFS2_FIRST_BANK 0
  185. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  186. /* 512k reserved for u-boot */
  187. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
  188. #define CONFIG_BOOTCOMMAND "run flashboot"
  189. #define CONFIG_CON_ROT "fbcon=rotate:3 "
  190. #define CONFIG_EXTRA_ENV_SETTINGS \
  191. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  192. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  193. "partition=nand0,0\0" \
  194. "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  195. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  196. CONFIG_CON_ROT \
  197. "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
  198. "addip=setenv bootargs $(bootargs) " \
  199. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
  200. ":$(hostname):eth0:off\0" \
  201. "ramboot=tftpboot 0x22000000 vmImage;" \
  202. "run ramargs;run addip;bootm 22000000\0" \
  203. "nfsboot=tftpboot 0x22000000 vmImage;" \
  204. "run nfsargs;run addip;bootm 22000000\0" \
  205. "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
  206. ""
  207. #else
  208. #error "Undefined memory device"
  209. #endif
  210. /*
  211. * Size of malloc() pool
  212. */
  213. #define CONFIG_SYS_MALLOC_LEN \
  214. ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  215. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  216. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
  217. GENERATED_GBL_DATA_SIZE)
  218. #endif