p1_twr.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * QorIQ P1 Tower boards configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #if defined(CONFIG_TWR_P1025)
  11. #define CONFIG_BOARDNAME "TWR-P1025"
  12. #define CONFIG_PHY_ATHEROS
  13. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
  14. #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
  15. #endif
  16. #ifdef CONFIG_SDCARD
  17. #define CONFIG_RAMBOOT_SDCARD
  18. #define CONFIG_SYS_RAMBOOT
  19. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  20. #endif
  21. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  22. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  23. #endif
  24. #ifndef CONFIG_SYS_MONITOR_BASE
  25. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  26. #endif
  27. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  28. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  29. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  30. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  31. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  32. #define CONFIG_ENV_OVERWRITE
  33. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  34. #define CONFIG_LBA48
  35. #ifndef __ASSEMBLY__
  36. extern unsigned long get_board_sys_clk(unsigned long dummy);
  37. #endif
  38. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
  39. #define CONFIG_DDR_CLK_FREQ 66666666
  40. #define CONFIG_HWCONFIG
  41. /*
  42. * These can be toggled for performance analysis, otherwise use default.
  43. */
  44. #define CONFIG_L2_CACHE
  45. #define CONFIG_BTB
  46. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  47. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  48. #define CONFIG_SYS_CCSRBAR 0xffe00000
  49. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  50. /* DDR Setup */
  51. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
  52. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  53. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  54. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  55. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  56. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  57. /* Default settings for DDR3 */
  58. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
  59. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  60. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  61. #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
  62. #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
  63. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  64. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  65. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  66. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  67. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  68. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  69. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
  70. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  71. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  72. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  73. #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
  74. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  75. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  76. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  77. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  78. #define CONFIG_SYS_DDR_TIMING_0 0x00220004
  79. #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
  80. #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
  81. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  82. #define CONFIG_SYS_DDR_MODE_1 0x80461320
  83. #define CONFIG_SYS_DDR_MODE_2 0x00008000
  84. #define CONFIG_SYS_DDR_INTERVAL 0x09480000
  85. /*
  86. * Memory map
  87. *
  88. * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
  89. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
  90. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  91. *
  92. * Localbus
  93. * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
  94. * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
  95. *
  96. * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
  97. * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
  98. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  99. */
  100. /*
  101. * Local Bus Definitions
  102. */
  103. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  104. #define CONFIG_SYS_FLASH_BASE 0xec000000
  105. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  106. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
  107. | BR_PS_16 | BR_V)
  108. #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
  109. #define CONFIG_SYS_SSD_BASE 0xe0000000
  110. #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
  111. #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
  112. BR_PS_16 | BR_V)
  113. #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  114. OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
  115. OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
  116. #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
  117. #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
  118. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  119. #define CONFIG_SYS_FLASH_QUIET_TEST
  120. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  121. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  122. #undef CONFIG_SYS_FLASH_CHECKSUM
  123. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  124. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  125. #define CONFIG_SYS_FLASH_EMPTY_INFO
  126. #define CONFIG_SYS_INIT_RAM_LOCK
  127. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
  128. /* Initial L1 address */
  129. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  130. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  131. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  132. /* Size of used area in RAM */
  133. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  134. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  135. GENERATED_GBL_DATA_SIZE)
  136. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  137. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  138. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  139. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  140. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  141. /* Serial Port
  142. * open - index 2
  143. * shorted - index 1
  144. */
  145. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  146. #define CONFIG_SYS_NS16550_SERIAL
  147. #define CONFIG_SYS_NS16550_REG_SIZE 1
  148. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  149. #define CONFIG_SYS_BAUDRATE_TABLE \
  150. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  151. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  152. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  153. /* I2C */
  154. #define CONFIG_SYS_I2C
  155. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  156. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
  157. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  158. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  159. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  160. /*
  161. * I2C2 EEPROM
  162. */
  163. #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
  164. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  165. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  166. #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
  167. /* enable read and write access to EEPROM */
  168. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  169. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  170. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  171. #if defined(CONFIG_PCI)
  172. /*
  173. * General PCI
  174. * Memory space is mapped 1-1, but I/O space must start from 0.
  175. */
  176. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  177. #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
  178. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  179. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  180. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  181. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  182. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  183. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  184. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  185. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  186. /* controller 1, tgtid 1, Base address a000 */
  187. #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
  188. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  189. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  190. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  191. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  192. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  193. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  194. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  195. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  196. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  197. #endif /* CONFIG_PCI */
  198. #if defined(CONFIG_TSEC_ENET)
  199. #define CONFIG_TSEC1
  200. #define CONFIG_TSEC1_NAME "eTSEC1"
  201. #undef CONFIG_TSEC2
  202. #undef CONFIG_TSEC2_NAME
  203. #define CONFIG_TSEC3
  204. #define CONFIG_TSEC3_NAME "eTSEC3"
  205. #define TSEC1_PHY_ADDR 2
  206. #define TSEC2_PHY_ADDR 0
  207. #define TSEC3_PHY_ADDR 1
  208. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  209. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  210. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  211. #define TSEC1_PHYIDX 0
  212. #define TSEC2_PHYIDX 0
  213. #define TSEC3_PHYIDX 0
  214. #define CONFIG_ETHPRIME "eTSEC1"
  215. #define CONFIG_HAS_ETH0
  216. #define CONFIG_HAS_ETH1
  217. #undef CONFIG_HAS_ETH2
  218. #endif /* CONFIG_TSEC_ENET */
  219. #ifdef CONFIG_QE
  220. /* QE microcode/firmware address */
  221. #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
  222. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  223. #endif /* CONFIG_QE */
  224. #ifdef CONFIG_TWR_P1025
  225. /*
  226. * QE UEC ethernet configuration
  227. */
  228. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  229. #undef CONFIG_UEC_ETH
  230. #define CONFIG_PHY_MODE_NEED_CHANGE
  231. #define CONFIG_UEC_ETH1 /* ETH1 */
  232. #define CONFIG_HAS_ETH0
  233. #ifdef CONFIG_UEC_ETH1
  234. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  235. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
  236. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
  237. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  238. #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
  239. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  240. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  241. #endif /* CONFIG_UEC_ETH1 */
  242. #define CONFIG_UEC_ETH5 /* ETH5 */
  243. #define CONFIG_HAS_ETH1
  244. #ifdef CONFIG_UEC_ETH5
  245. #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
  246. #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
  247. #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
  248. #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
  249. #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
  250. #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  251. #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
  252. #endif /* CONFIG_UEC_ETH5 */
  253. #endif /* CONFIG_TWR-P1025 */
  254. /*
  255. * Dynamic MTD Partition support with mtdparts
  256. */
  257. /*
  258. * Environment
  259. */
  260. #ifdef CONFIG_SYS_RAMBOOT
  261. #ifdef CONFIG_RAMBOOT_SDCARD
  262. #define CONFIG_SYS_MMC_ENV_DEV 0
  263. #endif
  264. #endif
  265. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  266. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  267. /*
  268. * USB
  269. */
  270. #define CONFIG_HAS_FSL_DR_USB
  271. #if defined(CONFIG_HAS_FSL_DR_USB)
  272. #ifdef CONFIG_USB_EHCI_HCD
  273. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  274. #define CONFIG_USB_EHCI_FSL
  275. #endif
  276. #endif
  277. #ifdef CONFIG_MMC
  278. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  279. #endif
  280. #undef CONFIG_WATCHDOG /* watchdog disabled */
  281. /*
  282. * Miscellaneous configurable options
  283. */
  284. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  285. /*
  286. * For booting Linux, the board info and command line data
  287. * have to be in the first 64 MB of memory, since this is
  288. * the maximum mapped by the Linux kernel during initialization.
  289. */
  290. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  291. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  292. /*
  293. * Environment Configuration
  294. */
  295. #define CONFIG_HOSTNAME "unknown"
  296. #define CONFIG_ROOTPATH "/opt/nfsroot"
  297. #define CONFIG_BOOTFILE "uImage"
  298. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  299. /* default location for tftp and bootm */
  300. #define CONFIG_LOADADDR 1000000
  301. #define CONFIG_EXTRA_ENV_SETTINGS \
  302. "netdev=eth0\0" \
  303. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  304. "loadaddr=1000000\0" \
  305. "bootfile=uImage\0" \
  306. "dtbfile=twr-p1025twr.dtb\0" \
  307. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  308. "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
  309. "tftpflash=tftpboot $loadaddr $uboot; " \
  310. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  311. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  312. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  313. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  314. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  315. "kernelflash=tftpboot $loadaddr $bootfile; " \
  316. "protect off 0xefa80000 +$filesize; " \
  317. "erase 0xefa80000 +$filesize; " \
  318. "cp.b $loadaddr 0xefa80000 $filesize; " \
  319. "protect on 0xefa80000 +$filesize; " \
  320. "cmp.b $loadaddr 0xefa80000 $filesize\0" \
  321. "dtbflash=tftpboot $loadaddr $dtbfile; " \
  322. "protect off 0xefe80000 +$filesize; " \
  323. "erase 0xefe80000 +$filesize; " \
  324. "cp.b $loadaddr 0xefe80000 $filesize; " \
  325. "protect on 0xefe80000 +$filesize; " \
  326. "cmp.b $loadaddr 0xefe80000 $filesize\0" \
  327. "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
  328. "protect off 0xeeb80000 +$filesize; " \
  329. "erase 0xeeb80000 +$filesize; " \
  330. "cp.b $loadaddr 0xeeb80000 $filesize; " \
  331. "protect on 0xeeb80000 +$filesize; " \
  332. "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
  333. "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
  334. "protect off 0xefec0000 +$filesize; " \
  335. "erase 0xefec0000 +$filesize; " \
  336. "cp.b $loadaddr 0xefec0000 $filesize; " \
  337. "protect on 0xefec0000 +$filesize; " \
  338. "cmp.b $loadaddr 0xefec0000 $filesize\0" \
  339. "consoledev=ttyS0\0" \
  340. "ramdiskaddr=2000000\0" \
  341. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  342. "fdtaddr=1e00000\0" \
  343. "bdev=sda1\0" \
  344. "norbootaddr=ef080000\0" \
  345. "norfdtaddr=ef040000\0" \
  346. "ramdisk_size=120000\0" \
  347. "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
  348. "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
  349. #define CONFIG_NFSBOOTCOMMAND \
  350. "setenv bootargs root=/dev/nfs rw " \
  351. "nfsroot=$serverip:$rootpath " \
  352. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  353. "console=$consoledev,$baudrate $othbootargs;" \
  354. "tftp $loadaddr $bootfile&&" \
  355. "tftp $fdtaddr $fdtfile&&" \
  356. "bootm $loadaddr - $fdtaddr"
  357. #define CONFIG_HDBOOT \
  358. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  359. "console=$consoledev,$baudrate $othbootargs;" \
  360. "usb start;" \
  361. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  362. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  363. "bootm $loadaddr - $fdtaddr"
  364. #define CONFIG_USB_FAT_BOOT \
  365. "setenv bootargs root=/dev/ram rw " \
  366. "console=$consoledev,$baudrate $othbootargs " \
  367. "ramdisk_size=$ramdisk_size;" \
  368. "usb start;" \
  369. "fatload usb 0:2 $loadaddr $bootfile;" \
  370. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  371. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  372. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  373. #define CONFIG_USB_EXT2_BOOT \
  374. "setenv bootargs root=/dev/ram rw " \
  375. "console=$consoledev,$baudrate $othbootargs " \
  376. "ramdisk_size=$ramdisk_size;" \
  377. "usb start;" \
  378. "ext2load usb 0:4 $loadaddr $bootfile;" \
  379. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  380. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  381. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  382. #define CONFIG_NORBOOT \
  383. "setenv bootargs root=/dev/mtdblock3 rw " \
  384. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  385. "bootm $norbootaddr - $norfdtaddr"
  386. #define CONFIG_RAMBOOTCOMMAND_TFTP \
  387. "setenv bootargs root=/dev/ram rw " \
  388. "console=$consoledev,$baudrate $othbootargs " \
  389. "ramdisk_size=$ramdisk_size;" \
  390. "tftp $ramdiskaddr $ramdiskfile;" \
  391. "tftp $loadaddr $bootfile;" \
  392. "tftp $fdtaddr $fdtfile;" \
  393. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  394. #define CONFIG_RAMBOOTCOMMAND \
  395. "setenv bootargs root=/dev/ram rw " \
  396. "console=$consoledev,$baudrate $othbootargs " \
  397. "ramdisk_size=$ramdisk_size;" \
  398. "bootm 0xefa80000 0xeeb80000 0xefe80000"
  399. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  400. #endif /* __CONFIG_H */