p1_p2_rdb_pc.h 27 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * QorIQ RDB boards configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #if defined(CONFIG_TARGET_P1020MBG)
  11. #define CONFIG_BOARDNAME "P1020MBG-PC"
  12. #define CONFIG_VSC7385_ENET
  13. #define CONFIG_SLIC
  14. #define __SW_BOOT_MASK 0x03
  15. #define __SW_BOOT_NOR 0xe4
  16. #define __SW_BOOT_SD 0x54
  17. #define CONFIG_SYS_L2_SIZE (256 << 10)
  18. #endif
  19. #if defined(CONFIG_TARGET_P1020UTM)
  20. #define CONFIG_BOARDNAME "P1020UTM-PC"
  21. #define __SW_BOOT_MASK 0x03
  22. #define __SW_BOOT_NOR 0xe0
  23. #define __SW_BOOT_SD 0x50
  24. #define CONFIG_SYS_L2_SIZE (256 << 10)
  25. #endif
  26. #if defined(CONFIG_TARGET_P1020RDB_PC)
  27. #define CONFIG_BOARDNAME "P1020RDB-PC"
  28. #define CONFIG_NAND_FSL_ELBC
  29. #define CONFIG_VSC7385_ENET
  30. #define CONFIG_SLIC
  31. #define __SW_BOOT_MASK 0x03
  32. #define __SW_BOOT_NOR 0x5c
  33. #define __SW_BOOT_SPI 0x1c
  34. #define __SW_BOOT_SD 0x9c
  35. #define __SW_BOOT_NAND 0xec
  36. #define __SW_BOOT_PCIE 0x6c
  37. #define CONFIG_SYS_L2_SIZE (256 << 10)
  38. #endif
  39. /*
  40. * P1020RDB-PD board has user selectable switches for evaluating different
  41. * frequency and boot options for the P1020 device. The table that
  42. * follow describe the available options. The front six binary number was in
  43. * accordance with SW3[1:6].
  44. * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  45. * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  46. * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  47. * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  48. * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  49. * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  50. * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  51. */
  52. #if defined(CONFIG_TARGET_P1020RDB_PD)
  53. #define CONFIG_BOARDNAME "P1020RDB-PD"
  54. #define CONFIG_NAND_FSL_ELBC
  55. #define CONFIG_VSC7385_ENET
  56. #define CONFIG_SLIC
  57. #define __SW_BOOT_MASK 0x03
  58. #define __SW_BOOT_NOR 0x64
  59. #define __SW_BOOT_SPI 0x34
  60. #define __SW_BOOT_SD 0x24
  61. #define __SW_BOOT_NAND 0x44
  62. #define __SW_BOOT_PCIE 0x74
  63. #define CONFIG_SYS_L2_SIZE (256 << 10)
  64. /*
  65. * Dynamic MTD Partition support with mtdparts
  66. */
  67. #endif
  68. #if defined(CONFIG_TARGET_P1021RDB)
  69. #define CONFIG_BOARDNAME "P1021RDB-PC"
  70. #define CONFIG_NAND_FSL_ELBC
  71. #define CONFIG_VSC7385_ENET
  72. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  73. addresses in the LBC */
  74. #define __SW_BOOT_MASK 0x03
  75. #define __SW_BOOT_NOR 0x5c
  76. #define __SW_BOOT_SPI 0x1c
  77. #define __SW_BOOT_SD 0x9c
  78. #define __SW_BOOT_NAND 0xec
  79. #define __SW_BOOT_PCIE 0x6c
  80. #define CONFIG_SYS_L2_SIZE (256 << 10)
  81. /*
  82. * Dynamic MTD Partition support with mtdparts
  83. */
  84. #endif
  85. #if defined(CONFIG_TARGET_P1024RDB)
  86. #define CONFIG_BOARDNAME "P1024RDB"
  87. #define CONFIG_NAND_FSL_ELBC
  88. #define CONFIG_SLIC
  89. #define __SW_BOOT_MASK 0xf3
  90. #define __SW_BOOT_NOR 0x00
  91. #define __SW_BOOT_SPI 0x08
  92. #define __SW_BOOT_SD 0x04
  93. #define __SW_BOOT_NAND 0x0c
  94. #define CONFIG_SYS_L2_SIZE (256 << 10)
  95. #endif
  96. #if defined(CONFIG_TARGET_P1025RDB)
  97. #define CONFIG_BOARDNAME "P1025RDB"
  98. #define CONFIG_NAND_FSL_ELBC
  99. #define CONFIG_SLIC
  100. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  101. addresses in the LBC */
  102. #define __SW_BOOT_MASK 0xf3
  103. #define __SW_BOOT_NOR 0x00
  104. #define __SW_BOOT_SPI 0x08
  105. #define __SW_BOOT_SD 0x04
  106. #define __SW_BOOT_NAND 0x0c
  107. #define CONFIG_SYS_L2_SIZE (256 << 10)
  108. #endif
  109. #if defined(CONFIG_TARGET_P2020RDB)
  110. #define CONFIG_BOARDNAME "P2020RDB-PC"
  111. #define CONFIG_NAND_FSL_ELBC
  112. #define CONFIG_VSC7385_ENET
  113. #define __SW_BOOT_MASK 0x03
  114. #define __SW_BOOT_NOR 0xc8
  115. #define __SW_BOOT_SPI 0x28
  116. #define __SW_BOOT_SD 0x68 /* or 0x18 */
  117. #define __SW_BOOT_NAND 0xe8
  118. #define __SW_BOOT_PCIE 0xa8
  119. #define CONFIG_SYS_L2_SIZE (512 << 10)
  120. /*
  121. * Dynamic MTD Partition support with mtdparts
  122. */
  123. #endif
  124. #ifdef CONFIG_SDCARD
  125. #define CONFIG_SPL_FLUSH_IMAGE
  126. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  127. #define CONFIG_SPL_PAD_TO 0x20000
  128. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  129. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  130. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  131. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  132. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  133. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  134. #ifdef CONFIG_SPL_BUILD
  135. #define CONFIG_SPL_COMMON_INIT_DDR
  136. #endif
  137. #endif
  138. #ifdef CONFIG_SPIFLASH
  139. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  140. #define CONFIG_SPL_FLUSH_IMAGE
  141. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  142. #define CONFIG_SPL_PAD_TO 0x20000
  143. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  144. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  145. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  146. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  147. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  148. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  149. #ifdef CONFIG_SPL_BUILD
  150. #define CONFIG_SPL_COMMON_INIT_DDR
  151. #endif
  152. #endif
  153. #ifdef CONFIG_MTD_RAW_NAND
  154. #ifdef CONFIG_TPL_BUILD
  155. #define CONFIG_SPL_FLUSH_IMAGE
  156. #define CONFIG_SPL_NAND_INIT
  157. #define CONFIG_SPL_COMMON_INIT_DDR
  158. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  159. #define CONFIG_TPL_TEXT_BASE 0xf8f81000
  160. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  161. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  162. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  163. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  164. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  165. #elif defined(CONFIG_SPL_BUILD)
  166. #define CONFIG_SPL_INIT_MINIMAL
  167. #define CONFIG_SPL_FLUSH_IMAGE
  168. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  169. #define CONFIG_SPL_MAX_SIZE 4096
  170. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  171. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  172. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  173. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  174. #endif /* not CONFIG_TPL_BUILD */
  175. #define CONFIG_SPL_PAD_TO 0x20000
  176. #define CONFIG_TPL_PAD_TO 0x20000
  177. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  178. #endif
  179. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  180. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  181. #endif
  182. #ifndef CONFIG_SYS_MONITOR_BASE
  183. #ifdef CONFIG_TPL_BUILD
  184. #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
  185. #elif defined(CONFIG_SPL_BUILD)
  186. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  187. #else
  188. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  189. #endif
  190. #endif
  191. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  192. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  193. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  194. #define CONFIG_ENV_OVERWRITE
  195. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  196. #define CONFIG_LBA48
  197. #if defined(CONFIG_TARGET_P2020RDB)
  198. #define CONFIG_SYS_CLK_FREQ 100000000
  199. #else
  200. #define CONFIG_SYS_CLK_FREQ 66666666
  201. #endif
  202. #define CONFIG_DDR_CLK_FREQ 66666666
  203. #define CONFIG_HWCONFIG
  204. /*
  205. * These can be toggled for performance analysis, otherwise use default.
  206. */
  207. #define CONFIG_L2_CACHE
  208. #define CONFIG_BTB
  209. #define CONFIG_ENABLE_36BIT_PHYS
  210. #ifdef CONFIG_PHYS_64BIT
  211. #define CONFIG_ADDR_MAP 1
  212. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  213. #endif
  214. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  215. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  216. #define CONFIG_SYS_CCSRBAR 0xffe00000
  217. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  218. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  219. SPL code*/
  220. #ifdef CONFIG_SPL_BUILD
  221. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  222. #endif
  223. /* DDR Setup */
  224. #define CONFIG_SYS_DDR_RAW_TIMING
  225. #define CONFIG_DDR_SPD
  226. #define CONFIG_SYS_SPD_BUS_NUM 1
  227. #define SPD_EEPROM_ADDRESS 0x52
  228. #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  229. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  230. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  231. #else
  232. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
  233. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  234. #endif
  235. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  236. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  237. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  238. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  239. /* Default settings for DDR3 */
  240. #ifndef CONFIG_TARGET_P2020RDB
  241. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  242. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  243. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  244. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  245. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  246. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  247. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  248. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  249. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  250. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  251. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  252. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  253. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  254. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  255. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  256. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  257. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  258. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  259. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  260. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  261. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  262. #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  263. #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  264. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  265. #define CONFIG_SYS_DDR_MODE_1 0x40461520
  266. #define CONFIG_SYS_DDR_MODE_2 0x8000c000
  267. #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  268. #endif
  269. #undef CONFIG_CLOCKS_IN_MHZ
  270. /*
  271. * Memory map
  272. *
  273. * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  274. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
  275. * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  276. * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
  277. * (early boot only)
  278. * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
  279. * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
  280. * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
  281. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
  282. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  283. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  284. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  285. */
  286. /*
  287. * Local Bus Definitions
  288. */
  289. #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  290. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  291. #define CONFIG_SYS_FLASH_BASE 0xec000000
  292. #elif defined(CONFIG_TARGET_P1020UTM)
  293. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  294. #define CONFIG_SYS_FLASH_BASE 0xee000000
  295. #else
  296. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
  297. #define CONFIG_SYS_FLASH_BASE 0xef000000
  298. #endif
  299. #ifdef CONFIG_PHYS_64BIT
  300. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  301. #else
  302. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  303. #endif
  304. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  305. | BR_PS_16 | BR_V)
  306. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  307. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  308. #define CONFIG_SYS_FLASH_QUIET_TEST
  309. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  310. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  311. #undef CONFIG_SYS_FLASH_CHECKSUM
  312. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  313. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  314. #define CONFIG_SYS_FLASH_EMPTY_INFO
  315. /* Nand Flash */
  316. #ifdef CONFIG_NAND_FSL_ELBC
  317. #define CONFIG_SYS_NAND_BASE 0xff800000
  318. #ifdef CONFIG_PHYS_64BIT
  319. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  320. #else
  321. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  322. #endif
  323. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  324. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  325. #if defined(CONFIG_TARGET_P1020RDB_PD)
  326. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  327. #else
  328. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  329. #endif
  330. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  331. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  332. | BR_PS_8 /* Port Size = 8 bit */ \
  333. | BR_MS_FCM /* MSEL = FCM */ \
  334. | BR_V) /* valid */
  335. #if defined(CONFIG_TARGET_P1020RDB_PD)
  336. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
  337. | OR_FCM_PGS /* Large Page*/ \
  338. | OR_FCM_CSCT \
  339. | OR_FCM_CST \
  340. | OR_FCM_CHT \
  341. | OR_FCM_SCY_1 \
  342. | OR_FCM_TRLX \
  343. | OR_FCM_EHTR)
  344. #else
  345. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
  346. | OR_FCM_CSCT \
  347. | OR_FCM_CST \
  348. | OR_FCM_CHT \
  349. | OR_FCM_SCY_1 \
  350. | OR_FCM_TRLX \
  351. | OR_FCM_EHTR)
  352. #endif
  353. #endif /* CONFIG_NAND_FSL_ELBC */
  354. #define CONFIG_SYS_INIT_RAM_LOCK
  355. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  356. #ifdef CONFIG_PHYS_64BIT
  357. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  358. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  359. /* The assembler doesn't like typecast */
  360. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  361. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  362. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  363. #else
  364. /* Initial L1 address */
  365. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  366. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  367. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  368. #endif
  369. /* Size of used area in RAM */
  370. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  371. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  372. GENERATED_GBL_DATA_SIZE)
  373. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  374. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  375. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  376. #define CONFIG_SYS_CPLD_BASE 0xffa00000
  377. #ifdef CONFIG_PHYS_64BIT
  378. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
  379. #else
  380. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  381. #endif
  382. /* CPLD config size: 1Mb */
  383. #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
  384. BR_PS_8 | BR_V)
  385. #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
  386. #define CONFIG_SYS_PMC_BASE 0xff980000
  387. #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  388. #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  389. BR_PS_8 | BR_V)
  390. #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  391. OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  392. OR_GPCM_EAD)
  393. #ifdef CONFIG_MTD_RAW_NAND
  394. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  395. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  396. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  397. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  398. #else
  399. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  400. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  401. #ifdef CONFIG_NAND_FSL_ELBC
  402. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  403. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  404. #endif
  405. #endif
  406. #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
  407. #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
  408. /* Vsc7385 switch */
  409. #ifdef CONFIG_VSC7385_ENET
  410. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  411. #ifdef CONFIG_PHYS_64BIT
  412. #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
  413. #else
  414. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  415. #endif
  416. #define CONFIG_SYS_VSC7385_BR_PRELIM \
  417. (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
  418. #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
  419. OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
  420. OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
  421. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
  422. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
  423. /* The size of the VSC7385 firmware image */
  424. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  425. #endif
  426. /*
  427. * Config the L2 Cache as L2 SRAM
  428. */
  429. #if defined(CONFIG_SPL_BUILD)
  430. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  431. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  432. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  433. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  434. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  435. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  436. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  437. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  438. #if defined(CONFIG_TARGET_P2020RDB)
  439. #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
  440. #else
  441. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  442. #endif
  443. #elif defined(CONFIG_MTD_RAW_NAND)
  444. #ifdef CONFIG_TPL_BUILD
  445. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  446. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  447. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  448. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  449. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  450. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  451. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  452. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  453. #else
  454. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  455. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  456. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  457. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  458. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  459. #endif /* CONFIG_TPL_BUILD */
  460. #endif
  461. #endif
  462. /* Serial Port - controlled on board with jumper J8
  463. * open - index 2
  464. * shorted - index 1
  465. */
  466. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  467. #define CONFIG_SYS_NS16550_SERIAL
  468. #define CONFIG_SYS_NS16550_REG_SIZE 1
  469. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  470. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  471. #define CONFIG_NS16550_MIN_FUNCTIONS
  472. #endif
  473. #define CONFIG_SYS_BAUDRATE_TABLE \
  474. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  475. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  476. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  477. /* I2C */
  478. #define CONFIG_SYS_I2C
  479. #define CONFIG_SYS_I2C_FSL
  480. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  481. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  482. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  483. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  484. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  485. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  486. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  487. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  488. #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  489. /*
  490. * I2C2 EEPROM
  491. */
  492. #undef CONFIG_ID_EEPROM
  493. #define CONFIG_RTC_PT7C4338
  494. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  495. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  496. /* enable read and write access to EEPROM */
  497. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  498. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  499. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  500. #if defined(CONFIG_PCI)
  501. /*
  502. * General PCI
  503. * Memory space is mapped 1-1, but I/O space must start from 0.
  504. */
  505. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  506. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  507. #ifdef CONFIG_PHYS_64BIT
  508. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  509. #else
  510. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  511. #endif
  512. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  513. #ifdef CONFIG_PHYS_64BIT
  514. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  515. #else
  516. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  517. #endif
  518. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  519. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  520. #ifdef CONFIG_PHYS_64BIT
  521. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  522. #else
  523. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  524. #endif
  525. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  526. #ifdef CONFIG_PHYS_64BIT
  527. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  528. #else
  529. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  530. #endif
  531. #if !defined(CONFIG_DM_PCI)
  532. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  533. #define CONFIG_PCI_INDIRECT_BRIDGE
  534. #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
  535. #ifdef CONFIG_PHYS_64BIT
  536. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  537. #else
  538. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  539. #endif
  540. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  541. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  542. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  543. #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
  544. #ifdef CONFIG_PHYS_64BIT
  545. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  546. #else
  547. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  548. #endif
  549. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  550. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  551. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  552. #endif
  553. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  554. #endif /* CONFIG_PCI */
  555. #if defined(CONFIG_TSEC_ENET)
  556. #define CONFIG_TSEC1
  557. #define CONFIG_TSEC1_NAME "eTSEC1"
  558. #define CONFIG_TSEC2
  559. #define CONFIG_TSEC2_NAME "eTSEC2"
  560. #define CONFIG_TSEC3
  561. #define CONFIG_TSEC3_NAME "eTSEC3"
  562. #define TSEC1_PHY_ADDR 2
  563. #define TSEC2_PHY_ADDR 0
  564. #define TSEC3_PHY_ADDR 1
  565. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  566. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  567. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  568. #define TSEC1_PHYIDX 0
  569. #define TSEC2_PHYIDX 0
  570. #define TSEC3_PHYIDX 0
  571. #define CONFIG_ETHPRIME "eTSEC1"
  572. #define CONFIG_HAS_ETH0
  573. #define CONFIG_HAS_ETH1
  574. #define CONFIG_HAS_ETH2
  575. #endif /* CONFIG_TSEC_ENET */
  576. #ifdef CONFIG_QE
  577. /* QE microcode/firmware address */
  578. #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
  579. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  580. #endif /* CONFIG_QE */
  581. #ifdef CONFIG_TARGET_P1025RDB
  582. /*
  583. * QE UEC ethernet configuration
  584. */
  585. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  586. #undef CONFIG_UEC_ETH
  587. #define CONFIG_PHY_MODE_NEED_CHANGE
  588. #define CONFIG_UEC_ETH1 /* ETH1 */
  589. #define CONFIG_HAS_ETH0
  590. #ifdef CONFIG_UEC_ETH1
  591. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  592. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
  593. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
  594. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  595. #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
  596. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  597. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  598. #endif /* CONFIG_UEC_ETH1 */
  599. #define CONFIG_UEC_ETH5 /* ETH5 */
  600. #define CONFIG_HAS_ETH1
  601. #ifdef CONFIG_UEC_ETH5
  602. #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
  603. #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
  604. #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
  605. #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
  606. #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
  607. #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  608. #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
  609. #endif /* CONFIG_UEC_ETH5 */
  610. #endif /* CONFIG_TARGET_P1025RDB */
  611. /*
  612. * Environment
  613. */
  614. #if defined(CONFIG_SDCARD)
  615. #define CONFIG_FSL_FIXED_MMC_LOCATION
  616. #define CONFIG_SYS_MMC_ENV_DEV 0
  617. #elif defined(CONFIG_MTD_RAW_NAND)
  618. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  619. #ifdef CONFIG_TPL_BUILD
  620. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  621. #endif
  622. #elif defined(CONFIG_SYS_RAMBOOT)
  623. #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  624. #endif
  625. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  626. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  627. /*
  628. * USB
  629. */
  630. #define CONFIG_HAS_FSL_DR_USB
  631. #if defined(CONFIG_HAS_FSL_DR_USB)
  632. #ifdef CONFIG_USB_EHCI_HCD
  633. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  634. #define CONFIG_USB_EHCI_FSL
  635. #endif
  636. #endif
  637. #if defined(CONFIG_TARGET_P1020RDB_PD)
  638. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  639. #endif
  640. #ifdef CONFIG_MMC
  641. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  642. #endif
  643. #undef CONFIG_WATCHDOG /* watchdog disabled */
  644. /*
  645. * Miscellaneous configurable options
  646. */
  647. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  648. /*
  649. * For booting Linux, the board info and command line data
  650. * have to be in the first 64 MB of memory, since this is
  651. * the maximum mapped by the Linux kernel during initialization.
  652. */
  653. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  654. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  655. #if defined(CONFIG_CMD_KGDB)
  656. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  657. #endif
  658. /*
  659. * Environment Configuration
  660. */
  661. #define CONFIG_HOSTNAME "unknown"
  662. #define CONFIG_ROOTPATH "/opt/nfsroot"
  663. #define CONFIG_BOOTFILE "uImage"
  664. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  665. /* default location for tftp and bootm */
  666. #define CONFIG_LOADADDR 1000000
  667. #ifdef __SW_BOOT_NOR
  668. #define __NOR_RST_CMD \
  669. norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
  670. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  671. #endif
  672. #ifdef __SW_BOOT_SPI
  673. #define __SPI_RST_CMD \
  674. spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
  675. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  676. #endif
  677. #ifdef __SW_BOOT_SD
  678. #define __SD_RST_CMD \
  679. sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
  680. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  681. #endif
  682. #ifdef __SW_BOOT_NAND
  683. #define __NAND_RST_CMD \
  684. nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
  685. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  686. #endif
  687. #ifdef __SW_BOOT_PCIE
  688. #define __PCIE_RST_CMD \
  689. pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
  690. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  691. #endif
  692. #define CONFIG_EXTRA_ENV_SETTINGS \
  693. "netdev=eth0\0" \
  694. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  695. "loadaddr=1000000\0" \
  696. "bootfile=uImage\0" \
  697. "tftpflash=tftpboot $loadaddr $uboot; " \
  698. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  699. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  700. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  701. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  702. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  703. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  704. "consoledev=ttyS0\0" \
  705. "ramdiskaddr=2000000\0" \
  706. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  707. "fdtaddr=1e00000\0" \
  708. "bdev=sda1\0" \
  709. "jffs2nor=mtdblock3\0" \
  710. "norbootaddr=ef080000\0" \
  711. "norfdtaddr=ef040000\0" \
  712. "jffs2nand=mtdblock9\0" \
  713. "nandbootaddr=100000\0" \
  714. "nandfdtaddr=80000\0" \
  715. "ramdisk_size=120000\0" \
  716. "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
  717. "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
  718. __stringify(__NOR_RST_CMD)"\0" \
  719. __stringify(__SPI_RST_CMD)"\0" \
  720. __stringify(__SD_RST_CMD)"\0" \
  721. __stringify(__NAND_RST_CMD)"\0" \
  722. __stringify(__PCIE_RST_CMD)"\0"
  723. #define CONFIG_NFSBOOTCOMMAND \
  724. "setenv bootargs root=/dev/nfs rw " \
  725. "nfsroot=$serverip:$rootpath " \
  726. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  727. "console=$consoledev,$baudrate $othbootargs;" \
  728. "tftp $loadaddr $bootfile;" \
  729. "tftp $fdtaddr $fdtfile;" \
  730. "bootm $loadaddr - $fdtaddr"
  731. #define CONFIG_HDBOOT \
  732. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  733. "console=$consoledev,$baudrate $othbootargs;" \
  734. "usb start;" \
  735. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  736. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  737. "bootm $loadaddr - $fdtaddr"
  738. #define CONFIG_USB_FAT_BOOT \
  739. "setenv bootargs root=/dev/ram rw " \
  740. "console=$consoledev,$baudrate $othbootargs " \
  741. "ramdisk_size=$ramdisk_size;" \
  742. "usb start;" \
  743. "fatload usb 0:2 $loadaddr $bootfile;" \
  744. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  745. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  746. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  747. #define CONFIG_USB_EXT2_BOOT \
  748. "setenv bootargs root=/dev/ram rw " \
  749. "console=$consoledev,$baudrate $othbootargs " \
  750. "ramdisk_size=$ramdisk_size;" \
  751. "usb start;" \
  752. "ext2load usb 0:4 $loadaddr $bootfile;" \
  753. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  754. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  755. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  756. #define CONFIG_NORBOOT \
  757. "setenv bootargs root=/dev/$jffs2nor rw " \
  758. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  759. "bootm $norbootaddr - $norfdtaddr"
  760. #define CONFIG_RAMBOOTCOMMAND \
  761. "setenv bootargs root=/dev/ram rw " \
  762. "console=$consoledev,$baudrate $othbootargs " \
  763. "ramdisk_size=$ramdisk_size;" \
  764. "tftp $ramdiskaddr $ramdiskfile;" \
  765. "tftp $loadaddr $bootfile;" \
  766. "tftp $fdtaddr $fdtfile;" \
  767. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  768. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  769. #endif /* __CONFIG_H */