omapl138_lcdk.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on davinci_dvevm.h. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * Board
  13. */
  14. /*
  15. * SoC Configuration
  16. */
  17. #define CONFIG_MACH_OMAPL138_LCDK
  18. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  19. #define CONFIG_SYS_OSCIN_FREQ 24000000
  20. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  21. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  22. #define CONFIG_SYS_HZ 1000
  23. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  24. /*
  25. * Memory Info
  26. */
  27. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  28. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  29. #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
  30. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  31. #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  32. #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  33. /* memtest start addr */
  34. #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
  35. /* memtest will be run on 16MB */
  36. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  37. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  38. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  39. DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
  40. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  41. DAVINCI_SYSCFG_SUSPSRC_EMAC | \
  42. DAVINCI_SYSCFG_SUSPSRC_I2C)
  43. /*
  44. * PLL configuration
  45. */
  46. /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  47. #define CONFIG_SYS_DA850_PLL0_PLLM 18
  48. #define CONFIG_SYS_DA850_PLL1_PLLM 21
  49. /*
  50. * DDR2 memory configuration
  51. */
  52. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  53. DV_DDR_PHY_EXT_STRBEN | \
  54. (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  55. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  56. (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
  57. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  58. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  59. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  60. (4 << DV_DDR_SDCR_CL_SHIFT) | \
  61. (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
  62. (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  63. /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  64. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  65. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  66. (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  67. (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
  68. (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  69. (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
  70. (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  71. (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
  72. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  73. (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  74. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  75. (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  76. (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
  77. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  78. (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  79. (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  80. (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  81. (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  82. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
  83. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
  84. /*
  85. * Serial Driver info
  86. */
  87. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  88. #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
  89. #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
  90. /*
  91. * I2C Configuration
  92. */
  93. #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
  94. #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
  95. #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
  96. /*
  97. * Flash & Environment
  98. */
  99. #ifdef CONFIG_MTD_RAW_NAND
  100. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  101. #define CONFIG_SYS_NAND_PAGE_2K
  102. #define CONFIG_SYS_NAND_CS 3
  103. #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
  104. #define CONFIG_SYS_NAND_MASK_CLE 0x10
  105. #define CONFIG_SYS_NAND_MASK_ALE 0x8
  106. #undef CONFIG_SYS_NAND_HW_ECC
  107. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  108. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  109. #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
  110. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  111. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
  112. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  113. #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
  114. #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
  115. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  116. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
  117. CONFIG_SYS_NAND_U_BOOT_SIZE - \
  118. CONFIG_SYS_MALLOC_LEN - \
  119. GENERATED_GBL_DATA_SIZE)
  120. #define CONFIG_SYS_NAND_ECCPOS { \
  121. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
  122. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
  123. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
  124. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
  125. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  126. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  127. #define CONFIG_SYS_NAND_ECCSIZE 512
  128. #define CONFIG_SYS_NAND_ECCBYTES 10
  129. #define CONFIG_SYS_NAND_OOBSIZE 64
  130. #define CONFIG_SPL_NAND_BASE
  131. #define CONFIG_SPL_NAND_DRIVERS
  132. #define CONFIG_SPL_NAND_ECC
  133. #define CONFIG_SPL_NAND_LOAD
  134. #endif
  135. /*
  136. * Network & Ethernet Configuration
  137. */
  138. #ifdef CONFIG_DRIVER_TI_EMAC
  139. #undef CONFIG_DRIVER_TI_EMAC_USE_RMII
  140. #define CONFIG_BOOTP_DEFAULT
  141. #define CONFIG_BOOTP_DNS2
  142. #define CONFIG_BOOTP_SEND_HOSTNAME
  143. #define CONFIG_NET_RETRY_COUNT 10
  144. #endif
  145. /*
  146. * U-Boot general configuration
  147. */
  148. #define CONFIG_BOOTFILE "zImage" /* Boot file name */
  149. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  150. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  151. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  152. /*
  153. * USB Configs
  154. */
  155. #define CONFIG_USB_OHCI_NEW
  156. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  157. /*
  158. * Linux Information
  159. */
  160. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  161. #define CONFIG_CMDLINE_TAG
  162. #define CONFIG_REVISION_TAG
  163. #define CONFIG_SETUP_MEMORY_TAGS
  164. #define CONFIG_BOOTCOMMAND \
  165. "run envboot; " \
  166. "run mmcboot; "
  167. #define DEFAULT_LINUX_BOOT_ENV \
  168. "loadaddr=0xc0700000\0" \
  169. "fdtaddr=0xc0600000\0" \
  170. "scriptaddr=0xc0600000\0"
  171. #include <environment/ti/mmc.h>
  172. #define CONFIG_EXTRA_ENV_SETTINGS \
  173. DEFAULT_LINUX_BOOT_ENV \
  174. DEFAULT_MMC_TI_ARGS \
  175. "bootpart=0:2\0" \
  176. "bootdir=/boot\0" \
  177. "bootfile=zImage\0" \
  178. "fdtfile=da850-lcdk.dtb\0" \
  179. "boot_fdt=yes\0" \
  180. "boot_fit=0\0" \
  181. "console=ttyS2,115200n8\0"
  182. #ifdef CONFIG_CMD_BDI
  183. #define CONFIG_CLOCKS
  184. #endif
  185. /* SD/MMC */
  186. /* defines for SPL */
  187. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  188. CONFIG_SYS_MALLOC_LEN)
  189. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  190. #define CONFIG_SPL_STACK 0x8001ff00
  191. #define CONFIG_SPL_MAX_FOOTPRINT 32768
  192. #define CONFIG_SPL_PAD_TO 32768
  193. /* additions for new relocation code, must added to all boards */
  194. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  195. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
  196. GENERATED_GBL_DATA_SIZE)
  197. #include <asm/arch/hardware.h>
  198. #endif /* __CONFIG_H */