mx31pdk.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
  4. *
  5. * (C) Copyright 2004
  6. * Texas Instruments.
  7. * Richard Woodruff <r-woodruff2@ti.com>
  8. * Kshitij Gupta <kshitij@ti.com>
  9. *
  10. * Configuration settings for the Freescale i.MX31 PDK board.
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. #include <asm/arch/imx-regs.h>
  15. /* High Level Configuration Options */
  16. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  17. #define CONFIG_SETUP_MEMORY_TAGS
  18. #define CONFIG_INITRD_TAG
  19. #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
  20. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  21. #define CONFIG_SPL_MAX_SIZE 2048
  22. #ifndef CONFIG_SPL_BUILD
  23. #define CONFIG_SKIP_LOWLEVEL_INIT
  24. #endif
  25. /*
  26. * Size of malloc() pool
  27. */
  28. #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
  29. /*
  30. * Hardware drivers
  31. */
  32. #define CONFIG_MXC_UART
  33. #define CONFIG_MXC_UART_BASE UART1_BASE
  34. /* PMIC Controller */
  35. #define CONFIG_POWER
  36. #define CONFIG_POWER_SPI
  37. #define CONFIG_POWER_FSL
  38. #define CONFIG_FSL_PMIC_BUS 1
  39. #define CONFIG_FSL_PMIC_CS 2
  40. #define CONFIG_FSL_PMIC_CLK 1000000
  41. #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
  42. #define CONFIG_FSL_PMIC_BITLEN 32
  43. #define CONFIG_RTC_MC13XXX
  44. /* allow to overwrite serial and ethaddr */
  45. #define CONFIG_ENV_OVERWRITE
  46. #define CONFIG_EXTRA_ENV_SETTINGS \
  47. "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
  48. "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
  49. "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
  50. "bootcmd=run bootcmd_net\0" \
  51. "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
  52. "tftpboot 0x81000000 uImage-mx31; bootm\0" \
  53. "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
  54. "nand erase 0x0 0x40000; " \
  55. "nand write 0x81000000 0x0 0x40000\0"
  56. /*
  57. * Miscellaneous configurable options
  58. */
  59. /* memtest works on */
  60. #define CONFIG_SYS_MEMTEST_START 0x80000000
  61. #define CONFIG_SYS_MEMTEST_END 0x80010000
  62. /* default load address */
  63. #define CONFIG_SYS_LOAD_ADDR 0x81000000
  64. /*-----------------------------------------------------------------------
  65. * Physical Memory Map
  66. */
  67. #define PHYS_SDRAM_1 CSD0_BASE
  68. #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
  69. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  70. #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  71. #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  72. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  73. GENERATED_GBL_DATA_SIZE)
  74. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  75. CONFIG_SYS_INIT_RAM_SIZE)
  76. /*
  77. * environment organization
  78. */
  79. /*
  80. * NAND driver
  81. */
  82. #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
  83. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  84. #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
  85. #define CONFIG_MXC_NAND_HWECC
  86. #define CONFIG_SYS_NAND_LARGEPAGE
  87. /* NAND configuration for the NAND_SPL */
  88. /* Start copying real U-Boot from the second page */
  89. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  90. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
  91. /* Load U-Boot to this address */
  92. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  93. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  94. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  95. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  96. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  97. #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
  98. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  99. /* Configuration of lowlevel_init.S (clocks and SDRAM) */
  100. #define CCM_CCMR_SETUP 0x074B0BF5
  101. #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
  102. PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
  103. PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
  104. PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
  105. #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
  106. PLL_MFN(12))
  107. #define ESDMISC_MDDR_SETUP 0x00000004
  108. #define ESDMISC_MDDR_RESET_DL 0x0000000c
  109. #define ESDCFG0_MDDR_SETUP 0x006ac73a
  110. #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
  111. #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
  112. ESDCTL_DSIZ(2) | ESDCTL_BL(1))
  113. #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
  114. #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
  115. #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
  116. #define ESDCTL_RW ESDCTL_SETTINGS
  117. #endif /* __CONFIG_H */