meesc.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2009-2015
  8. * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  9. * esd electronic system design gmbh <www.esd.eu>
  10. *
  11. * Configuation settings for the esd MEESC board.
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. /*
  16. * SoC must be defined first, before hardware.h is included.
  17. * In this case SoC is defined in boards.cfg.
  18. */
  19. #include <asm/hardware.h>
  20. /*
  21. * Warning: changing CONFIG_SYS_TEXT_BASE requires
  22. * adapting the initial boot program.
  23. * Since the linker has to swallow that define, we must use a pure
  24. * hex number here!
  25. */
  26. /* ARM asynchronous clock */
  27. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
  28. #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
  29. /* Misc CPU related */
  30. #define CONFIG_SKIP_LOWLEVEL_INIT
  31. #define CONFIG_SETUP_MEMORY_TAGS
  32. #define CONFIG_INITRD_TAG
  33. #define CONFIG_SERIAL_TAG
  34. #define CONFIG_REVISION_TAG
  35. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  36. /*
  37. * Hardware drivers
  38. */
  39. /*
  40. * BOOTP options
  41. */
  42. #define CONFIG_BOOTP_BOOTFILESIZE
  43. /*
  44. * SDRAM: 1 bank, min 32, max 128 MB
  45. * Initialized before u-boot gets started.
  46. */
  47. #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
  48. #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
  49. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  50. #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
  51. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
  52. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
  53. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
  54. /*
  55. * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  56. * leaving the correct space for initial global data structure above
  57. * that address while providing maximum stack area below.
  58. */
  59. #define CONFIG_SYS_INIT_SP_ADDR \
  60. (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  61. /* NAND flash */
  62. #ifdef CONFIG_CMD_NAND
  63. # define CONFIG_SYS_MAX_NAND_DEVICE 1
  64. # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
  65. # define CONFIG_SYS_NAND_DBW_8
  66. # define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  67. # define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  68. # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
  69. # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
  70. #endif
  71. /* Ethernet */
  72. #define CONFIG_MACB
  73. #define CONFIG_RMII
  74. #define CONFIG_NET_RETRY_COUNT 20
  75. #undef CONFIG_RESET_PHY_R
  76. /* hw-controller addresses */
  77. #define CONFIG_ET1100_BASE 0x70000000
  78. #ifdef CONFIG_SYS_USE_DATAFLASH
  79. /* bootstrap + u-boot + env in dataflash on CS0 */
  80. #elif CONFIG_SYS_USE_NANDFLASH
  81. /* bootstrap + u-boot + env + linux in nandflash */
  82. #endif
  83. #define CONFIG_SYS_CBSIZE 512
  84. /*
  85. * Size of malloc() pool
  86. */
  87. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
  88. 128*1024, 0x1000)
  89. #endif