maxbcm.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. */
  5. #ifndef _CONFIG_DB_MV7846MP_GP_H
  6. #define _CONFIG_DB_MV7846MP_GP_H
  7. /*
  8. * High Level Configuration Options (easy to change)
  9. */
  10. /*
  11. * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  12. * for DDR ECC byte filling in the SPL before loading the main
  13. * U-Boot into it.
  14. */
  15. #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  16. /*
  17. * Commands configuration
  18. */
  19. /* I2C */
  20. #define CONFIG_SYS_I2C
  21. #define CONFIG_SYS_I2C_MVTWSI
  22. #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
  23. #define CONFIG_SYS_I2C_SLAVE 0x0
  24. #define CONFIG_SYS_I2C_SPEED 100000
  25. /* SPI NOR flash default params, used by sf commands */
  26. /* Environment in SPI NOR flash */
  27. #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
  28. /*
  29. * mv-common.h should be defined after CMD configs since it used them
  30. * to enable certain macros
  31. */
  32. #include "mv-common.h"
  33. /*
  34. * Memory layout while starting into the bin_hdr via the
  35. * BootROM:
  36. *
  37. * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
  38. * 0x4000.4030 bin_hdr start address
  39. * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
  40. * 0x4007.fffc BootROM stack top
  41. *
  42. * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  43. * L2 cache thus cannot be used.
  44. */
  45. /* SPL */
  46. /* Defines for SPL */
  47. #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
  48. #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
  49. #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
  50. #ifdef CONFIG_SPL_BUILD
  51. #define CONFIG_SYS_MALLOC_SIMPLE
  52. #endif
  53. #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
  54. #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
  55. /* SPL related SPI defines */
  56. /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  57. #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
  58. #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
  59. #endif /* _CONFIG_DB_MV7846MP_GP_H */