lx2160aqds.h 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2019 NXP
  4. */
  5. #ifndef __LX2_QDS_H
  6. #define __LX2_QDS_H
  7. #include "lx2160a_common.h"
  8. /* Qixis */
  9. #define QIXIS_XMAP_MASK 0x07
  10. #define QIXIS_XMAP_SHIFT 5
  11. #define QIXIS_RST_CTL_RESET_EN 0x30
  12. #define QIXIS_LBMAP_DFLTBANK 0x00
  13. #define QIXIS_LBMAP_ALTBANK 0x20
  14. #define QIXIS_LBMAP_QSPI 0x00
  15. #define QIXIS_RCW_SRC_QSPI 0xff
  16. #define QIXIS_RST_CTL_RESET 0x31
  17. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  18. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  19. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  20. #define QIXIS_LBMAP_MASK 0x0f
  21. #define QIXIS_LBMAP_SD
  22. #define QIXIS_RCW_SRC_SD 0x08
  23. #define NON_EXTENDED_DUTCFG
  24. #define QIXIS_SDID_MASK 0x07
  25. #define QIXIS_ESDHC_NO_ADAPTER 0x7
  26. /* SYSCLK */
  27. #define QIXIS_SYSCLK_100 0x0
  28. #define QIXIS_SYSCLK_125 0x1
  29. #define QIXIS_SYSCLK_133 0x2
  30. /* DDRCLK */
  31. #define QIXIS_DDRCLK_100 0x0
  32. #define QIXIS_DDRCLK_125 0x1
  33. #define QIXIS_DDRCLK_133 0x2
  34. #define BRDCFG4_EMI1SEL_MASK 0xF8
  35. #define BRDCFG4_EMI1SEL_SHIFT 3
  36. #define BRDCFG4_EMI2SEL_MASK 0x07
  37. #define BRDCFG4_EMI2SEL_SHIFT 0
  38. /* VID */
  39. #define I2C_MUX_CH_VOL_MONITOR 0xA
  40. /* Voltage monitor on channel 2*/
  41. #define I2C_VOL_MONITOR_ADDR 0x63
  42. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  43. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  44. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  45. #define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
  46. #define CONFIG_VID
  47. /* The lowest and highest voltage allowed*/
  48. #define VDD_MV_MIN 775
  49. #define VDD_MV_MAX 925
  50. /* PM Bus commands code for LTC3882*/
  51. #define PMBUS_CMD_PAGE 0x0
  52. #define PMBUS_CMD_READ_VOUT 0x8B
  53. #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
  54. #define PMBUS_CMD_VOUT_COMMAND 0x21
  55. #define PWM_CHANNEL0 0x0
  56. #define CONFIG_VOL_MONITOR_LTC3882_SET
  57. #define CONFIG_VOL_MONITOR_LTC3882_READ
  58. /* RTC */
  59. #define CONFIG_SYS_RTC_BUS_NUM 0
  60. #define I2C_MUX_CH_RTC 0xB
  61. /*
  62. * MMC
  63. */
  64. #ifdef CONFIG_MMC
  65. #ifndef __ASSEMBLY__
  66. u8 qixis_esdhc_detect_quirk(void);
  67. #endif
  68. #define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
  69. #endif
  70. /* MAC/PHY configuration */
  71. #if defined(CONFIG_FSL_MC_ENET)
  72. #define CONFIG_MII
  73. #define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
  74. #define AQ_PHY_ADDR1 0x00
  75. #define AQ_PHY_ADDR2 0x01
  76. #define AQ_PHY_ADDR3 0x02
  77. #define AQ_PHY_ADDR4 0x03
  78. #define CORTINA_NO_FW_UPLOAD
  79. #define CORTINA_PHY_ADDR1 0x0
  80. #define INPHI_PHY_ADDR1 0x0
  81. #define INPHI_PHY_ADDR2 0x1
  82. #define RGMII_PHY_ADDR1 0x01
  83. #define RGMII_PHY_ADDR2 0x02
  84. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  85. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  86. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  87. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  88. #endif
  89. /* EEPROM */
  90. #define CONFIG_ID_EEPROM
  91. #define CONFIG_SYS_I2C_EEPROM_NXID
  92. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  93. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  94. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  95. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  96. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  97. /* Initial environment variables */
  98. #define CONFIG_EXTRA_ENV_SETTINGS \
  99. EXTRA_ENV_SETTINGS \
  100. "lx2160aqds_vdd_mv=800\0" \
  101. "BOARD=lx2160aqds\0" \
  102. "xspi_bootcmd=echo Trying load from flexspi..;" \
  103. "sf probe 0:0 && sf read $load_addr " \
  104. "$kernel_start $kernel_size ; env exists secureboot &&" \
  105. "sf read $kernelheader_addr_r $kernelheader_start " \
  106. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  107. " bootm $load_addr#$BOARD\0" \
  108. "sd_bootcmd=echo Trying load from sd card..;" \
  109. "mmcinfo; mmc read $load_addr " \
  110. "$kernel_addr_sd $kernel_size_sd ;" \
  111. "env exists secureboot && mmc read $kernelheader_addr_r "\
  112. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  113. " && esbc_validate ${kernelheader_addr_r};" \
  114. "bootm $load_addr#$BOARD\0"
  115. #include <asm/fsl_secure_boot.h>
  116. #endif /* __LX2_QDS_H */