lx2160a_common.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2019 NXP
  4. */
  5. #ifndef __LX2_COMMON_H
  6. #define __LX2_COMMON_H
  7. #include <asm/arch/stream_id_lsch3.h>
  8. #include <asm/arch/config.h>
  9. #include <asm/arch/soc.h>
  10. #define CONFIG_REMAKE_ELF
  11. #define CONFIG_FSL_LAYERSCAPE
  12. #define CONFIG_GICV3
  13. #define CONFIG_FSL_TZPC_BP147
  14. #define CONFIG_FSL_MEMAC
  15. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  16. #define CONFIG_SYS_FLASH_BASE 0x20000000
  17. #define CONFIG_SKIP_LOWLEVEL_INIT
  18. #define CONFIG_BOARD_EARLY_INIT_F 1
  19. /* DDR */
  20. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  21. #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
  22. #define CONFIG_VERY_BIG_RAM
  23. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  24. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  25. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
  26. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
  27. #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
  28. #define CONFIG_DDR_SPD
  29. #define CONFIG_DDR_ECC
  30. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  31. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  32. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  33. #define SPD_EEPROM_ADDRESS1 0x51
  34. #define SPD_EEPROM_ADDRESS2 0x52
  35. #define SPD_EEPROM_ADDRESS3 0x53
  36. #define SPD_EEPROM_ADDRESS4 0x54
  37. #define SPD_EEPROM_ADDRESS5 0x55
  38. #define SPD_EEPROM_ADDRESS6 0x56
  39. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  40. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  41. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  42. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  43. #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
  44. #define CONFIG_SYS_MONITOR_LEN (936 * 1024)
  45. /* Miscellaneous configurable options */
  46. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  47. /* SMP Definitinos */
  48. #define CPU_RELEASE_ADDR secondary_boot_func
  49. /* Generic Timer Definitions */
  50. /*
  51. * This is not an accurate number. It is used in start.S. The frequency
  52. * will be udpated later when get_bus_freq(0) is available.
  53. */
  54. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  55. /* Size of malloc() pool */
  56. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  57. /* Serial Port */
  58. #define CONFIG_PL01X_SERIAL
  59. #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
  60. #define CONFIG_SYS_SERIAL0 0x21c0000
  61. #define CONFIG_SYS_SERIAL1 0x21d0000
  62. #define CONFIG_SYS_SERIAL2 0x21e0000
  63. #define CONFIG_SYS_SERIAL3 0x21f0000
  64. /*below might needs to be removed*/
  65. #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
  66. (void *)CONFIG_SYS_SERIAL1, \
  67. (void *)CONFIG_SYS_SERIAL2, \
  68. (void *)CONFIG_SYS_SERIAL3 }
  69. #define CONFIG_BAUDRATE 115200
  70. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  71. /* MC firmware */
  72. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  73. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  74. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  75. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  76. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  77. /* Define phy_reset function to boot the MC based on mcinitcmd.
  78. * This happens late enough to properly fixup u-boot env MAC addresses.
  79. */
  80. #define CONFIG_RESET_PHY_R
  81. /*
  82. * Carve out a DDR region which will not be used by u-boot/Linux
  83. *
  84. * It will be used by MC and Debug Server. The MC region must be
  85. * 512MB aligned, so the min size to hide is 512MB.
  86. */
  87. #ifdef CONFIG_FSL_MC_ENET
  88. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
  89. #endif
  90. /* I2C bus multiplexer */
  91. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  92. #define I2C_MUX_CH_DEFAULT 0x8
  93. /* RTC */
  94. #define RTC
  95. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  96. /* EEPROM */
  97. #define CONFIG_ID_EEPROM
  98. #define CONFIG_SYS_I2C_EEPROM_NXID
  99. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  100. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  101. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  102. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  103. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  104. /* Qixis */
  105. #define CONFIG_FSL_QIXIS
  106. #define CONFIG_QIXIS_I2C_ACCESS
  107. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  108. /* PCI */
  109. #ifdef CONFIG_PCI
  110. #define CONFIG_SYS_PCI_64BIT
  111. #define CONFIG_PCI_SCAN_SHOW
  112. #endif
  113. /* MMC */
  114. #ifdef CONFIG_MMC
  115. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  116. #endif
  117. /* SATA */
  118. #ifdef CONFIG_SCSI
  119. #define CONFIG_SCSI_AHCI_PLAT
  120. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  121. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  122. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  123. #define CONFIG_SYS_SCSI_MAX_LUN 1
  124. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  125. CONFIG_SYS_SCSI_MAX_LUN)
  126. #endif
  127. /* USB */
  128. #ifdef CONFIG_USB
  129. #define CONFIG_HAS_FSL_XHCI_USB
  130. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  131. #endif
  132. /* FlexSPI */
  133. #ifdef CONFIG_NXP_FSPI
  134. #define NXP_FSPI_FLASH_SIZE SZ_64M
  135. #define NXP_FSPI_FLASH_NUM 1
  136. #endif
  137. #ifndef __ASSEMBLY__
  138. unsigned long get_board_sys_clk(void);
  139. unsigned long get_board_ddr_clk(void);
  140. #endif
  141. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  142. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  143. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
  144. #define CONFIG_HWCONFIG
  145. #define HWCONFIG_BUFFER_SIZE 128
  146. #define CONFIG_SYS_MMC_ENV_DEV 0
  147. /* Allow to overwrite serial and ethaddr */
  148. #define CONFIG_ENV_OVERWRITE
  149. /* Monitor Command Prompt */
  150. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  151. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  152. sizeof(CONFIG_SYS_PROMPT) + 16)
  153. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  154. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  155. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  156. /* Initial environment variables */
  157. #define XSPI_MC_INIT_CMD \
  158. "env exists secureboot && " \
  159. "esbc_validate 0x20700000 && " \
  160. "esbc_validate 0x20740000 ;" \
  161. "fsl_mc start mc 0x20a00000 0x20e00000\0"
  162. #define SD_MC_INIT_CMD \
  163. "mmc read 0x80a00000 0x5000 0x1200;" \
  164. "mmc read 0x80e00000 0x7000 0x800;" \
  165. "env exists secureboot && " \
  166. "mmc read 0x80700000 0x3800 0x10 && " \
  167. "mmc read 0x80740000 0x3A00 0x10 && " \
  168. "esbc_validate 0x80700000 && " \
  169. "esbc_validate 0x80740000 ;" \
  170. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  171. #define EXTRA_ENV_SETTINGS \
  172. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  173. "ramdisk_addr=0x800000\0" \
  174. "ramdisk_size=0x2000000\0" \
  175. "fdt_high=0xa0000000\0" \
  176. "initrd_high=0xffffffffffffffff\0" \
  177. "fdt_addr=0x64f00000\0" \
  178. "kernel_start=0x1000000\0" \
  179. "kernelheader_start=0x7C0000\0" \
  180. "scriptaddr=0x80000000\0" \
  181. "scripthdraddr=0x80080000\0" \
  182. "fdtheader_addr_r=0x80100000\0" \
  183. "kernelheader_addr_r=0x80200000\0" \
  184. "kernel_addr_r=0x81000000\0" \
  185. "kernelheader_size=0x40000\0" \
  186. "fdt_addr_r=0x90000000\0" \
  187. "load_addr=0xa0000000\0" \
  188. "kernel_size=0x2800000\0" \
  189. "kernel_addr_sd=0x8000\0" \
  190. "kernelhdr_addr_sd=0x3E00\0" \
  191. "kernel_size_sd=0x1d000\0" \
  192. "kernelhdr_size_sd=0x10\0" \
  193. "console=ttyAMA0,38400n8\0" \
  194. BOOTENV \
  195. "mcmemsize=0x70000000\0" \
  196. XSPI_MC_INIT_CMD \
  197. "boot_scripts=lx2160ardb_boot.scr\0" \
  198. "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
  199. "scan_dev_for_boot_part=" \
  200. "part list ${devtype} ${devnum} devplist; " \
  201. "env exists devplist || setenv devplist 1; " \
  202. "for distro_bootpart in ${devplist}; do " \
  203. "if fstype ${devtype} " \
  204. "${devnum}:${distro_bootpart} " \
  205. "bootfstype; then " \
  206. "run scan_dev_for_boot; " \
  207. "fi; " \
  208. "done\0" \
  209. "boot_a_script=" \
  210. "load ${devtype} ${devnum}:${distro_bootpart} " \
  211. "${scriptaddr} ${prefix}${script}; " \
  212. "env exists secureboot && load ${devtype} " \
  213. "${devnum}:${distro_bootpart} " \
  214. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  215. "&& esbc_validate ${scripthdraddr};" \
  216. "source ${scriptaddr}\0"
  217. #define XSPI_NOR_BOOTCOMMAND \
  218. "env exists mcinitcmd && env exists secureboot "\
  219. "&& esbc_validate 0x20780000; " \
  220. "env exists mcinitcmd && " \
  221. "fsl_mc lazyapply dpl 0x20d00000; " \
  222. "run distro_bootcmd;run xspi_bootcmd; " \
  223. "env exists secureboot && esbc_halt;"
  224. #define SD_BOOTCOMMAND \
  225. "env exists mcinitcmd && mmcinfo; " \
  226. "mmc read 0x80d00000 0x6800 0x800; " \
  227. "env exists mcinitcmd && env exists secureboot " \
  228. " && mmc read 0x80780000 0x3C00 0x10 " \
  229. "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  230. "&& fsl_mc lazyapply dpl 0x80d00000;" \
  231. "run distro_bootcmd;run sd_bootcmd;" \
  232. "env exists secureboot && esbc_halt;"
  233. #define BOOT_TARGET_DEVICES(func) \
  234. func(USB, usb, 0) \
  235. func(MMC, mmc, 0) \
  236. func(SCSI, scsi, 0)
  237. #include <config_distro_bootcmd.h>
  238. #endif /* __LX2_COMMON_H */