ls2080ardb.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017, 2019 NXP
  4. * Copyright 2015 Freescale Semiconductor
  5. */
  6. #ifndef __LS2_RDB_H
  7. #define __LS2_RDB_H
  8. #include "ls2080a_common.h"
  9. #ifdef CONFIG_FSL_QSPI
  10. #ifdef CONFIG_TARGET_LS2081ARDB
  11. #define CONFIG_QIXIS_I2C_ACCESS
  12. #endif
  13. #ifndef CONFIG_DM_I2C
  14. #define CONFIG_SYS_I2C_EARLY_INIT
  15. #endif
  16. #endif
  17. #define I2C_MUX_CH_VOL_MONITOR 0xa
  18. #define I2C_VOL_MONITOR_ADDR 0x38
  19. #define CONFIG_VOL_MONITOR_IR36021_READ
  20. #define CONFIG_VOL_MONITOR_IR36021_SET
  21. #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
  22. #ifndef CONFIG_SPL_BUILD
  23. #define CONFIG_VID
  24. #endif
  25. /* step the IR regulator in 5mV increments */
  26. #define IR_VDD_STEP_DOWN 5
  27. #define IR_VDD_STEP_UP 5
  28. /* The lowest and highest voltage allowed for LS2080ARDB */
  29. #define VDD_MV_MIN 819
  30. #define VDD_MV_MAX 1212
  31. #ifndef __ASSEMBLY__
  32. unsigned long get_board_sys_clk(void);
  33. #endif
  34. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  35. #define CONFIG_DDR_CLK_FREQ 133333333
  36. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  37. #define CONFIG_DDR_SPD
  38. #define CONFIG_DDR_ECC
  39. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  40. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  41. #define SPD_EEPROM_ADDRESS1 0x51
  42. #define SPD_EEPROM_ADDRESS2 0x52
  43. #define SPD_EEPROM_ADDRESS3 0x53
  44. #define SPD_EEPROM_ADDRESS4 0x54
  45. #define SPD_EEPROM_ADDRESS5 0x55
  46. #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
  47. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  48. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  49. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  50. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  51. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  52. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  53. #endif
  54. /* SATA */
  55. #define CONFIG_SCSI_AHCI_PLAT
  56. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  57. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  58. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  59. #define CONFIG_SYS_SCSI_MAX_LUN 1
  60. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  61. CONFIG_SYS_SCSI_MAX_LUN)
  62. #ifdef CONFIG_TFABOOT
  63. #define CONFIG_SYS_MMC_ENV_DEV 0
  64. #endif
  65. #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  66. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  67. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  68. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  69. #define CONFIG_SYS_NOR0_CSPR \
  70. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  71. CSPR_PORT_SIZE_16 | \
  72. CSPR_MSEL_NOR | \
  73. CSPR_V)
  74. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  75. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  76. CSPR_PORT_SIZE_16 | \
  77. CSPR_MSEL_NOR | \
  78. CSPR_V)
  79. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  80. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  81. FTIM0_NOR_TEADC(0x5) | \
  82. FTIM0_NOR_TEAHC(0x5))
  83. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  84. FTIM1_NOR_TRAD_NOR(0x1a) |\
  85. FTIM1_NOR_TSEQRAD_NOR(0x13))
  86. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  87. FTIM2_NOR_TCH(0x4) | \
  88. FTIM2_NOR_TWPH(0x0E) | \
  89. FTIM2_NOR_TWP(0x1c))
  90. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  91. #define CONFIG_SYS_IFC_CCR 0x01000000
  92. #ifdef CONFIG_MTD_NOR_FLASH
  93. #define CONFIG_SYS_FLASH_QUIET_TEST
  94. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  95. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  96. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  97. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  98. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  99. #define CONFIG_SYS_FLASH_EMPTY_INFO
  100. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  101. CONFIG_SYS_FLASH_BASE + 0x40000000}
  102. #endif
  103. #define CONFIG_NAND_FSL_IFC
  104. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  105. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  106. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  107. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  108. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  109. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  110. | CSPR_V)
  111. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  112. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  113. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  114. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  115. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  116. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  117. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  118. | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
  119. #define CONFIG_SYS_NAND_ONFI_DETECTION
  120. /* ONFI NAND Flash mode0 Timing Params */
  121. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
  122. FTIM0_NAND_TWP(0x30) | \
  123. FTIM0_NAND_TWCHT(0x0e) | \
  124. FTIM0_NAND_TWH(0x14))
  125. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
  126. FTIM1_NAND_TWBE(0xab) | \
  127. FTIM1_NAND_TRR(0x1c) | \
  128. FTIM1_NAND_TRP(0x30))
  129. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
  130. FTIM2_NAND_TREH(0x14) | \
  131. FTIM2_NAND_TWHRE(0x3c))
  132. #define CONFIG_SYS_NAND_FTIM3 0x0
  133. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  134. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  135. #define CONFIG_MTD_NAND_VERIFY_WRITE
  136. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  137. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  138. #define QIXIS_LBMAP_SWITCH 0x06
  139. #define QIXIS_LBMAP_MASK 0x0f
  140. #define QIXIS_LBMAP_SHIFT 0
  141. #define QIXIS_LBMAP_DFLTBANK 0x00
  142. #define QIXIS_LBMAP_ALTBANK 0x04
  143. #define QIXIS_LBMAP_NAND 0x09
  144. #define QIXIS_RST_CTL_RESET 0x31
  145. #define QIXIS_RST_CTL_RESET_EN 0x30
  146. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  147. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  148. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  149. #define QIXIS_RCW_SRC_NAND 0x119
  150. #define QIXIS_RST_FORCE_MEM 0x01
  151. #define CONFIG_SYS_CSPR3_EXT (0x0)
  152. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  153. | CSPR_PORT_SIZE_8 \
  154. | CSPR_MSEL_GPCM \
  155. | CSPR_V)
  156. #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  157. | CSPR_PORT_SIZE_8 \
  158. | CSPR_MSEL_GPCM \
  159. | CSPR_V)
  160. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  161. #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
  162. /* QIXIS Timing parameters for IFC CS3 */
  163. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  164. FTIM0_GPCM_TEADC(0x0e) | \
  165. FTIM0_GPCM_TEAHC(0x0e))
  166. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  167. FTIM1_GPCM_TRAD(0x3f))
  168. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  169. FTIM2_GPCM_TCH(0xf) | \
  170. FTIM2_GPCM_TWP(0x3E))
  171. #define CONFIG_SYS_CS3_FTIM3 0x0
  172. #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
  173. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  174. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
  175. #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
  176. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  177. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  178. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  179. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  180. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  181. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  182. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  183. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  184. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  185. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  186. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  187. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  188. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  189. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  190. #define CONFIG_SPL_PAD_TO 0x80000
  191. #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
  192. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
  193. #else
  194. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  195. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  196. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  197. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  198. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  199. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  200. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  201. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  202. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  203. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  204. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  205. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  206. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  207. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  208. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  209. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  210. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  211. #endif
  212. /* Debug Server firmware */
  213. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  214. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
  215. #endif
  216. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  217. #ifdef CONFIG_TARGET_LS2081ARDB
  218. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  219. #define QIXIS_QMAP_MASK 0x07
  220. #define QIXIS_QMAP_SHIFT 5
  221. #define QIXIS_LBMAP_DFLTBANK 0x00
  222. #define QIXIS_LBMAP_QSPI 0x00
  223. #define QIXIS_RCW_SRC_QSPI 0x62
  224. #define QIXIS_LBMAP_ALTBANK 0x20
  225. #define QIXIS_RST_CTL_RESET 0x31
  226. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  227. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  228. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  229. #define QIXIS_LBMAP_MASK 0x0f
  230. #define QIXIS_RST_CTL_RESET_EN 0x30
  231. #endif
  232. /*
  233. * I2C
  234. */
  235. #ifdef CONFIG_TARGET_LS2081ARDB
  236. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  237. #endif
  238. #define I2C_MUX_PCA_ADDR 0x75
  239. #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
  240. /* I2C bus multiplexer */
  241. #define I2C_MUX_CH_DEFAULT 0x8
  242. /* SPI */
  243. #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
  244. #ifdef CONFIG_FSL_DSPI
  245. #define CONFIG_SPI_FLASH_STMICRO
  246. #endif
  247. #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
  248. #define FSL_QSPI_FLASH_NUM 2
  249. #endif
  250. /*
  251. * RTC configuration
  252. */
  253. #define RTC
  254. #ifdef CONFIG_TARGET_LS2081ARDB
  255. #define CONFIG_RTC_PCF8563 1
  256. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  257. #else
  258. #define CONFIG_RTC_DS3231 1
  259. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  260. #endif
  261. /* EEPROM */
  262. #define CONFIG_ID_EEPROM
  263. #define CONFIG_SYS_I2C_EEPROM_NXID
  264. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  265. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  266. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  267. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  268. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  269. #define CONFIG_FSL_MEMAC
  270. #ifdef CONFIG_PCI
  271. #define CONFIG_PCI_SCAN_SHOW
  272. #endif
  273. /* MMC */
  274. #ifdef CONFIG_MMC
  275. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  276. #endif
  277. #define BOOT_TARGET_DEVICES(func) \
  278. func(USB, usb, 0) \
  279. func(MMC, mmc, 0) \
  280. func(SCSI, scsi, 0) \
  281. func(DHCP, dhcp, na)
  282. #include <config_distro_bootcmd.h>
  283. #ifdef CONFIG_TFABOOT
  284. #define QSPI_MC_INIT_CMD \
  285. "env exists secureboot && " \
  286. "esbc_validate 0x20700000 && " \
  287. "esbc_validate 0x20740000;" \
  288. "fsl_mc start mc 0x20a00000 0x20e00000 \0"
  289. #define SD_MC_INIT_CMD \
  290. "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
  291. "mmc read 0x80e00000 0x7000 0x800;" \
  292. "env exists secureboot && " \
  293. "mmc read 0x80700000 0x3800 0x10 && " \
  294. "mmc read 0x80740000 0x3A00 0x10 && " \
  295. "esbc_validate 0x80700000 && " \
  296. "esbc_validate 0x80740000 ;" \
  297. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  298. #define IFC_MC_INIT_CMD \
  299. "env exists secureboot && " \
  300. "esbc_validate 0x580700000 && " \
  301. "esbc_validate 0x580740000; " \
  302. "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  303. #else
  304. #ifdef CONFIG_QSPI_BOOT
  305. #define MC_INIT_CMD \
  306. "mcinitcmd=env exists secureboot && " \
  307. "esbc_validate 0x20700000 && " \
  308. "esbc_validate 0x20740000;" \
  309. "fsl_mc start mc 0x20a00000 0x20e00000 \0"
  310. #elif defined(CONFIG_SD_BOOT)
  311. #define MC_INIT_CMD \
  312. "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  313. "mmc read 0x80100000 0x7000 0x800;" \
  314. "env exists secureboot && " \
  315. "mmc read 0x80700000 0x3800 0x10 && " \
  316. "mmc read 0x80740000 0x3A00 0x10 && " \
  317. "esbc_validate 0x80700000 && " \
  318. "esbc_validate 0x80740000 ;" \
  319. "fsl_mc start mc 0x80000000 0x80100000\0" \
  320. "mcmemsize=0x70000000\0"
  321. #else
  322. #define MC_INIT_CMD \
  323. "mcinitcmd=env exists secureboot && " \
  324. "esbc_validate 0x580700000 && " \
  325. "esbc_validate 0x580740000; " \
  326. "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  327. #endif
  328. #endif
  329. /* Initial environment variables */
  330. #undef CONFIG_EXTRA_ENV_SETTINGS
  331. #ifdef CONFIG_TFABOOT
  332. #define CONFIG_EXTRA_ENV_SETTINGS \
  333. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  334. "ramdisk_addr=0x800000\0" \
  335. "ramdisk_size=0x2000000\0" \
  336. "fdt_high=0xa0000000\0" \
  337. "initrd_high=0xffffffffffffffff\0" \
  338. "fdt_addr=0x64f00000\0" \
  339. "kernel_addr=0x581000000\0" \
  340. "kernel_start=0x1000000\0" \
  341. "kernelheader_start=0x800000\0" \
  342. "scriptaddr=0x80000000\0" \
  343. "scripthdraddr=0x80080000\0" \
  344. "fdtheader_addr_r=0x80100000\0" \
  345. "kernelheader_addr_r=0x80200000\0" \
  346. "kernelheader_addr=0x580800000\0" \
  347. "kernel_addr_r=0x81000000\0" \
  348. "kernelheader_size=0x40000\0" \
  349. "fdt_addr_r=0x90000000\0" \
  350. "load_addr=0xa0000000\0" \
  351. "kernel_size=0x2800000\0" \
  352. "kernel_addr_sd=0x8000\0" \
  353. "kernel_size_sd=0x14000\0" \
  354. "console=ttyAMA0,38400n8\0" \
  355. "mcmemsize=0x70000000\0" \
  356. "sd_bootcmd=echo Trying load from SD ..;" \
  357. "mmcinfo; mmc read $load_addr " \
  358. "$kernel_addr_sd $kernel_size_sd && " \
  359. "bootm $load_addr#$board\0" \
  360. QSPI_MC_INIT_CMD \
  361. BOOTENV \
  362. "boot_scripts=ls2088ardb_boot.scr\0" \
  363. "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  364. "scan_dev_for_boot_part=" \
  365. "part list ${devtype} ${devnum} devplist; " \
  366. "env exists devplist || setenv devplist 1; " \
  367. "for distro_bootpart in ${devplist}; do " \
  368. "if fstype ${devtype} " \
  369. "${devnum}:${distro_bootpart} " \
  370. "bootfstype; then " \
  371. "run scan_dev_for_boot; " \
  372. "fi; " \
  373. "done\0" \
  374. "boot_a_script=" \
  375. "load ${devtype} ${devnum}:${distro_bootpart} " \
  376. "${scriptaddr} ${prefix}${script}; " \
  377. "env exists secureboot && load ${devtype} " \
  378. "${devnum}:${distro_bootpart} " \
  379. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  380. "&& esbc_validate ${scripthdraddr};" \
  381. "source ${scriptaddr}\0" \
  382. "qspi_bootcmd=echo Trying load from qspi..;" \
  383. "sf probe && sf read $load_addr " \
  384. "$kernel_start $kernel_size ; env exists secureboot &&" \
  385. "sf read $kernelheader_addr_r $kernelheader_start " \
  386. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  387. " bootm $load_addr#$board\0" \
  388. "nor_bootcmd=echo Trying load from nor..;" \
  389. "cp.b $kernel_addr $load_addr " \
  390. "$kernel_size ; env exists secureboot && " \
  391. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  392. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  393. "bootm $load_addr#$board\0"
  394. #else
  395. #define CONFIG_EXTRA_ENV_SETTINGS \
  396. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  397. "ramdisk_addr=0x800000\0" \
  398. "ramdisk_size=0x2000000\0" \
  399. "fdt_high=0xa0000000\0" \
  400. "initrd_high=0xffffffffffffffff\0" \
  401. "fdt_addr=0x64f00000\0" \
  402. "kernel_addr=0x581000000\0" \
  403. "kernel_start=0x1000000\0" \
  404. "kernelheader_start=0x800000\0" \
  405. "scriptaddr=0x80000000\0" \
  406. "scripthdraddr=0x80080000\0" \
  407. "fdtheader_addr_r=0x80100000\0" \
  408. "kernelheader_addr_r=0x80200000\0" \
  409. "kernelheader_addr=0x580800000\0" \
  410. "kernel_addr_r=0x81000000\0" \
  411. "kernelheader_size=0x40000\0" \
  412. "fdt_addr_r=0x90000000\0" \
  413. "load_addr=0xa0000000\0" \
  414. "kernel_size=0x2800000\0" \
  415. "kernel_addr_sd=0x8000\0" \
  416. "kernel_size_sd=0x14000\0" \
  417. "console=ttyAMA0,38400n8\0" \
  418. "mcmemsize=0x70000000\0" \
  419. "sd_bootcmd=echo Trying load from SD ..;" \
  420. "mmcinfo; mmc read $load_addr " \
  421. "$kernel_addr_sd $kernel_size_sd && " \
  422. "bootm $load_addr#$board\0" \
  423. MC_INIT_CMD \
  424. BOOTENV \
  425. "boot_scripts=ls2088ardb_boot.scr\0" \
  426. "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  427. "scan_dev_for_boot_part=" \
  428. "part list ${devtype} ${devnum} devplist; " \
  429. "env exists devplist || setenv devplist 1; " \
  430. "for distro_bootpart in ${devplist}; do " \
  431. "if fstype ${devtype} " \
  432. "${devnum}:${distro_bootpart} " \
  433. "bootfstype; then " \
  434. "run scan_dev_for_boot; " \
  435. "fi; " \
  436. "done\0" \
  437. "boot_a_script=" \
  438. "load ${devtype} ${devnum}:${distro_bootpart} " \
  439. "${scriptaddr} ${prefix}${script}; " \
  440. "env exists secureboot && load ${devtype} " \
  441. "${devnum}:${distro_bootpart} " \
  442. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  443. "env exists secureboot " \
  444. "&& esbc_validate ${scripthdraddr};" \
  445. "source ${scriptaddr}\0" \
  446. "qspi_bootcmd=echo Trying load from qspi..;" \
  447. "sf probe && sf read $load_addr " \
  448. "$kernel_start $kernel_size ; env exists secureboot &&" \
  449. "sf read $kernelheader_addr_r $kernelheader_start " \
  450. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  451. " bootm $load_addr#$board\0" \
  452. "nor_bootcmd=echo Trying load from nor..;" \
  453. "cp.b $kernel_addr $load_addr " \
  454. "$kernel_size ; env exists secureboot && " \
  455. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  456. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  457. "bootm $load_addr#$board\0"
  458. #endif
  459. #ifdef CONFIG_TFABOOT
  460. #define QSPI_NOR_BOOTCOMMAND \
  461. "env exists mcinitcmd && env exists secureboot "\
  462. "&& esbc_validate 0x20780000; " \
  463. "env exists mcinitcmd && " \
  464. "fsl_mc lazyapply dpl 0x20d00000; " \
  465. "run distro_bootcmd;run qspi_bootcmd; " \
  466. "env exists secureboot && esbc_halt;"
  467. /* Try to boot an on-SD kernel first, then do normal distro boot */
  468. #define SD_BOOTCOMMAND \
  469. "env exists mcinitcmd && env exists secureboot "\
  470. "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
  471. "&& esbc_validate $load_addr; " \
  472. "env exists mcinitcmd && run mcinitcmd " \
  473. "&& mmc read 0x80d00000 0x6800 0x800 " \
  474. "&& fsl_mc lazyapply dpl 0x80d00000; " \
  475. "run distro_bootcmd;run sd_bootcmd; " \
  476. "env exists secureboot && esbc_halt;"
  477. /* Try to boot an on-NOR kernel first, then do normal distro boot */
  478. #define IFC_NOR_BOOTCOMMAND \
  479. "env exists mcinitcmd && env exists secureboot "\
  480. "&& esbc_validate 0x580780000; env exists mcinitcmd "\
  481. "&& fsl_mc lazyapply dpl 0x580d00000;" \
  482. "run distro_bootcmd;run nor_bootcmd; " \
  483. "env exists secureboot && esbc_halt;"
  484. #else
  485. #undef CONFIG_BOOTCOMMAND
  486. #ifdef CONFIG_QSPI_BOOT
  487. /* Try to boot an on-QSPI kernel first, then do normal distro boot */
  488. #define CONFIG_BOOTCOMMAND \
  489. "env exists mcinitcmd && env exists secureboot "\
  490. "&& esbc_validate 0x20780000; " \
  491. "env exists mcinitcmd && " \
  492. "fsl_mc lazyapply dpl 0x20d00000; " \
  493. "run distro_bootcmd;run qspi_bootcmd; " \
  494. "env exists secureboot && esbc_halt;"
  495. #elif defined(CONFIG_SD_BOOT)
  496. /* Try to boot an on-SD kernel first, then do normal distro boot */
  497. #define CONFIG_BOOTCOMMAND \
  498. "env exists mcinitcmd && env exists secureboot "\
  499. "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
  500. "&& esbc_validate $load_addr; " \
  501. "env exists mcinitcmd && run mcinitcmd " \
  502. "&& mmc read 0x88000000 0x6800 0x800 " \
  503. "&& fsl_mc lazyapply dpl 0x88000000; " \
  504. "run distro_bootcmd;run sd_bootcmd; " \
  505. "env exists secureboot && esbc_halt;"
  506. #else
  507. /* Try to boot an on-NOR kernel first, then do normal distro boot */
  508. #define CONFIG_BOOTCOMMAND \
  509. "env exists mcinitcmd && env exists secureboot "\
  510. "&& esbc_validate 0x580780000; env exists mcinitcmd "\
  511. "&& fsl_mc lazyapply dpl 0x580d00000;" \
  512. "run distro_bootcmd;run nor_bootcmd; " \
  513. "env exists secureboot && esbc_halt;"
  514. #endif
  515. #endif
  516. /* MAC/PHY configuration */
  517. #ifdef CONFIG_FSL_MC_ENET
  518. #ifdef CONFIG_QSPI_BOOT
  519. #define CONFIG_CORTINA_FW_ADDR 0x20980000
  520. #else
  521. #define CONFIG_CORTINA_FW_ADDR 0x580980000
  522. #endif
  523. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  524. #define CORTINA_PHY_ADDR1 0x10
  525. #define CORTINA_PHY_ADDR2 0x11
  526. #define CORTINA_PHY_ADDR3 0x12
  527. #define CORTINA_PHY_ADDR4 0x13
  528. #define AQ_PHY_ADDR1 0x00
  529. #define AQ_PHY_ADDR2 0x01
  530. #define AQ_PHY_ADDR3 0x02
  531. #define AQ_PHY_ADDR4 0x03
  532. #define AQR405_IRQ_MASK 0x36
  533. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  534. #endif
  535. #include <asm/fsl_secure_boot.h>
  536. #endif /* __LS2_RDB_H */