ls2080a_simu.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor
  4. */
  5. #ifndef __LS2_SIMU_H
  6. #define __LS2_SIMU_H
  7. #include "ls2080a_common.h"
  8. #define CONFIG_SYS_CLK_FREQ 100000000
  9. #define CONFIG_DDR_CLK_FREQ 133333333
  10. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  11. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  12. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  13. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  14. #endif
  15. /* SMSC 91C111 ethernet configuration */
  16. #define CONFIG_SMC91111
  17. #define CONFIG_SMC91111_BASE (0x2210000)
  18. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  19. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  20. #ifdef CONFIG_MTD_NOR_FLASH
  21. #define CONFIG_SYS_FLASH_QUIET_TEST
  22. #endif
  23. /*
  24. * NOR Flash Timing Params
  25. */
  26. #define CONFIG_SYS_NOR0_CSPR \
  27. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  28. CSPR_PORT_SIZE_16 | \
  29. CSPR_MSEL_NOR | \
  30. CSPR_V)
  31. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  32. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  33. CSPR_PORT_SIZE_16 | \
  34. CSPR_MSEL_NOR | \
  35. CSPR_V)
  36. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  37. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  38. FTIM0_NOR_TEADC(0x1) | \
  39. FTIM0_NOR_TEAHC(0x1))
  40. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
  41. FTIM1_NOR_TRAD_NOR(0x1))
  42. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
  43. FTIM2_NOR_TCH(0x0) | \
  44. FTIM2_NOR_TWP(0x1))
  45. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  46. #define CONFIG_SYS_IFC_CCR 0x01000000
  47. #ifdef CONFIG_MTD_NOR_FLASH
  48. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  49. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  50. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  51. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  52. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  53. #define CONFIG_SYS_FLASH_EMPTY_INFO
  54. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  55. #endif
  56. #define CONFIG_NAND_FSL_IFC
  57. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  58. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  59. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  60. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  61. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  62. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  63. | CSPR_V)
  64. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  65. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  66. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  67. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  68. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  69. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  70. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  71. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  72. #define CONFIG_SYS_NAND_ONFI_DETECTION
  73. /* ONFI NAND Flash mode0 Timing Params */
  74. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  75. FTIM0_NAND_TWP(0x18) | \
  76. FTIM0_NAND_TWCHT(0x07) | \
  77. FTIM0_NAND_TWH(0x0a))
  78. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  79. FTIM1_NAND_TWBE(0x39) | \
  80. FTIM1_NAND_TRR(0x0e) | \
  81. FTIM1_NAND_TRP(0x18))
  82. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  83. FTIM2_NAND_TREH(0x0a) | \
  84. FTIM2_NAND_TWHRE(0x1e))
  85. #define CONFIG_SYS_NAND_FTIM3 0x0
  86. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  87. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  88. #define CONFIG_MTD_NAND_VERIFY_WRITE
  89. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  90. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  91. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  92. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  93. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  94. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  95. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  96. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  97. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  98. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  99. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  100. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  101. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  102. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  103. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  104. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  105. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  106. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  107. /* MMC */
  108. #ifdef CONFIG_MMC
  109. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  110. #endif
  111. /* Debug Server firmware */
  112. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  113. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
  114. /* MC firmware */
  115. #define CONFIG_SYS_LS_MC_DPL_IN_NOR
  116. #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
  117. #define CONFIG_SYS_LS_MC_DPC_IN_NOR
  118. #define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
  119. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
  120. /* Store environment at top of flash */
  121. #endif /* __LS2_SIMU_H */