ls2080a_emu.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor
  4. */
  5. #ifndef __LS2_EMU_H
  6. #define __LS2_EMU_H
  7. #include "ls2080a_common.h"
  8. #define CONFIG_SYS_CLK_FREQ 100000000
  9. #define CONFIG_DDR_CLK_FREQ 133333333
  10. #define CONFIG_DDR_SPD
  11. #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
  12. #define SPD_EEPROM_ADDRESS1 0x51
  13. #define SPD_EEPROM_ADDRESS2 0x52
  14. #define SPD_EEPROM_ADDRESS3 0x53
  15. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  16. #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
  17. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  18. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  19. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  20. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  21. #endif
  22. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  23. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  24. /*
  25. * NOR Flash Timing Params
  26. */
  27. #define CONFIG_SYS_NOR0_CSPR \
  28. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  29. CSPR_PORT_SIZE_16 | \
  30. CSPR_MSEL_NOR | \
  31. CSPR_V)
  32. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  33. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  34. CSPR_PORT_SIZE_16 | \
  35. CSPR_MSEL_NOR | \
  36. CSPR_V)
  37. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  38. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  39. FTIM0_NOR_TEADC(0x1) | \
  40. FTIM0_NOR_TEAHC(0x1))
  41. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
  42. FTIM1_NOR_TRAD_NOR(0x1))
  43. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
  44. FTIM2_NOR_TCH(0x0) | \
  45. FTIM2_NOR_TWP(0x1))
  46. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  47. #define CONFIG_SYS_IFC_CCR 0x01000000
  48. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  49. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  50. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  51. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  52. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  53. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  54. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  55. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  56. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  57. /* Debug Server firmware */
  58. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  59. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
  60. /*
  61. * This trick allows users to load MC images into DDR directly without
  62. * copying from NOR flash. It dramatically improves speed.
  63. */
  64. #define CONFIG_SYS_LS_MC_FW_IN_DDR
  65. #define CONFIG_SYS_LS_MC_DPL_IN_DDR
  66. #define CONFIG_SYS_LS_MC_DPC_IN_DDR
  67. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
  68. /* Store environment at top of flash */
  69. #endif /* __LS2_EMU_H */