ls2080a_common.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 NXP
  4. * Copyright (C) 2014 Freescale Semiconductor
  5. */
  6. #ifndef __LS2_COMMON_H
  7. #define __LS2_COMMON_H
  8. #define CONFIG_REMAKE_ELF
  9. #define CONFIG_GICV3
  10. #include <asm/arch/stream_id_lsch3.h>
  11. #include <asm/arch/config.h>
  12. /* Link Definitions */
  13. #ifdef CONFIG_TFABOOT
  14. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  15. #else
  16. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  17. #endif
  18. /* We need architecture specific misc initializations */
  19. /* Link Definitions */
  20. #define CONFIG_SKIP_LOWLEVEL_INIT
  21. #ifndef CONFIG_SYS_FSL_DDR4
  22. #define CONFIG_SYS_DDR_RAW_TIMING
  23. #endif
  24. #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
  25. #define CONFIG_VERY_BIG_RAM
  26. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  27. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  28. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  29. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
  30. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
  31. /*
  32. * SMP Definitinos
  33. */
  34. #define CPU_RELEASE_ADDR secondary_boot_func
  35. #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  36. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  37. #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
  38. /*
  39. * DDR controller use 0 as the base address for binding.
  40. * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  41. */
  42. #define CONFIG_SYS_DP_DDR_BASE_PHY 0
  43. #define CONFIG_DP_DDR_CTRL 2
  44. #define CONFIG_DP_DDR_NUM_CTRLS 1
  45. #endif
  46. /* Generic Timer Definitions */
  47. /*
  48. * This is not an accurate number. It is used in start.S. The frequency
  49. * will be udpated later when get_bus_freq(0) is available.
  50. */
  51. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  52. /* Size of malloc() pool */
  53. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  54. /* I2C */
  55. #ifndef CONFIG_DM_I2C
  56. #define CONFIG_SYS_I2C
  57. #endif
  58. /* Serial Port */
  59. #define CONFIG_SYS_NS16550_SERIAL
  60. #define CONFIG_SYS_NS16550_REG_SIZE 1
  61. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  62. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  63. /* IFC */
  64. #define CONFIG_FSL_IFC
  65. /*
  66. * During booting, IFC is mapped at the region of 0x30000000.
  67. * But this region is limited to 256MB. To accommodate NOR, promjet
  68. * and FPGA. This region is divided as below:
  69. * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  70. * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  71. * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  72. *
  73. * To accommodate bigger NOR flash and other devices, we will map IFC
  74. * chip selects to as below:
  75. * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  76. * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  77. * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  78. * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  79. * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  80. *
  81. * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  82. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  83. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  84. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  85. * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  86. */
  87. #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
  88. #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
  89. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  90. #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
  91. #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
  92. #ifndef __ASSEMBLY__
  93. unsigned long long get_qixis_addr(void);
  94. #endif
  95. #define QIXIS_BASE get_qixis_addr()
  96. #define QIXIS_BASE_PHYS 0x20000000
  97. #define QIXIS_BASE_PHYS_EARLY 0xC000000
  98. #define QIXIS_STAT_PRES1 0xb
  99. #define QIXIS_SDID_MASK 0x07
  100. #define QIXIS_ESDHC_NO_ADAPTER 0x7
  101. #define CONFIG_SYS_NAND_BASE 0x530000000ULL
  102. #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
  103. /* MC firmware */
  104. /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
  105. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  106. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  107. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  108. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  109. /* For LS2085A */
  110. #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
  111. #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
  112. /* Define phy_reset function to boot the MC based on mcinitcmd.
  113. * This happens late enough to properly fixup u-boot env MAC addresses.
  114. */
  115. #define CONFIG_RESET_PHY_R
  116. /*
  117. * Carve out a DDR region which will not be used by u-boot/Linux
  118. *
  119. * It will be used by MC and Debug Server. The MC region must be
  120. * 512MB aligned, so the min size to hide is 512MB.
  121. */
  122. #ifdef CONFIG_FSL_MC_ENET
  123. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
  124. #endif
  125. /* Command line configuration */
  126. /* Miscellaneous configurable options */
  127. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  128. /* Physical Memory Map */
  129. /* fixme: these need to be checked against the board */
  130. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  131. #define CONFIG_HWCONFIG
  132. #define HWCONFIG_BUFFER_SIZE 128
  133. /* Allow to overwrite serial and ethaddr */
  134. #define CONFIG_ENV_OVERWRITE
  135. /* Initial environment variables */
  136. #define CONFIG_EXTRA_ENV_SETTINGS \
  137. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  138. "loadaddr=0x80100000\0" \
  139. "kernel_addr=0x100000\0" \
  140. "ramdisk_addr=0x800000\0" \
  141. "ramdisk_size=0x2000000\0" \
  142. "fdt_high=0xa0000000\0" \
  143. "initrd_high=0xffffffffffffffff\0" \
  144. "kernel_start=0x581000000\0" \
  145. "kernel_load=0xa0000000\0" \
  146. "kernel_size=0x2800000\0" \
  147. "console=ttyAMA0,38400n8\0" \
  148. "mcinitcmd=fsl_mc start mc 0x580a00000" \
  149. " 0x580e00000 \0"
  150. #ifndef CONFIG_TFABOOT
  151. #ifdef CONFIG_SD_BOOT
  152. #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
  153. " fsl_mc apply dpl 0x80200000 &&" \
  154. " mmc read $kernel_load $kernel_start" \
  155. " $kernel_size && bootm $kernel_load"
  156. #else
  157. #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
  158. " cp.b $kernel_start $kernel_load" \
  159. " $kernel_size && bootm $kernel_load"
  160. #endif
  161. #endif
  162. /* Monitor Command Prompt */
  163. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  164. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  165. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  166. #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
  167. #define CONFIG_SPL_MAX_SIZE 0x16000
  168. #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
  169. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  170. #ifdef CONFIG_NAND_BOOT
  171. #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
  172. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  173. #endif
  174. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
  175. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  176. #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
  177. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  178. #include <asm/arch/soc.h>
  179. #endif /* __LS2_COMMON_H */