ls1088ardb.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #ifndef __LS1088A_RDB_H
  6. #define __LS1088A_RDB_H
  7. #include "ls1088a_common.h"
  8. #ifdef CONFIG_TFABOOT
  9. #define CONFIG_SYS_MMC_ENV_DEV 0
  10. #else
  11. #if defined(CONFIG_QSPI_BOOT)
  12. #elif defined(CONFIG_SD_BOOT)
  13. #define CONFIG_SYS_MMC_ENV_DEV 0
  14. #else
  15. #define CONFIG_ENV_IS_IN_FLASH
  16. #endif
  17. #endif /* CONFIG_TFABOOT */
  18. #if defined(CONFIG_TFABOOT) || \
  19. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  20. #ifndef CONFIG_SPL_BUILD
  21. #define CONFIG_QIXIS_I2C_ACCESS
  22. #endif
  23. #define SYS_NO_FLASH
  24. #undef CONFIG_CMD_IMLS
  25. #endif
  26. #define CONFIG_SYS_CLK_FREQ 100000000
  27. #define CONFIG_DDR_CLK_FREQ 100000000
  28. #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
  29. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  30. #define CONFIG_DDR_SPD
  31. #ifdef CONFIG_EMU
  32. #define CONFIG_SYS_FSL_DDR_EMU
  33. #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
  34. #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
  35. #else
  36. #define CONFIG_DDR_ECC
  37. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  38. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  39. #endif
  40. #define SPD_EEPROM_ADDRESS 0x51
  41. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  42. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  43. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  44. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  45. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  46. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
  47. #define CONFIG_SYS_NOR0_CSPR \
  48. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  49. CSPR_PORT_SIZE_16 | \
  50. CSPR_MSEL_NOR | \
  51. CSPR_V)
  52. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  53. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  54. CSPR_PORT_SIZE_16 | \
  55. CSPR_MSEL_NOR | \
  56. CSPR_V)
  57. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
  58. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  59. FTIM0_NOR_TEADC(0x1) | \
  60. FTIM0_NOR_TEAHC(0x1))
  61. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
  62. FTIM1_NOR_TRAD_NOR(0x1))
  63. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
  64. FTIM2_NOR_TCH(0x0) | \
  65. FTIM2_NOR_TWP(0x1))
  66. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  67. #define CONFIG_SYS_IFC_CCR 0x01000000
  68. #ifndef SYS_NO_FLASH
  69. #define CONFIG_SYS_FLASH_QUIET_TEST
  70. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  71. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  72. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  73. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  74. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  75. #define CONFIG_SYS_FLASH_EMPTY_INFO
  76. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  77. #endif
  78. #endif
  79. #ifndef SPL_NO_IFC
  80. #define CONFIG_NAND_FSL_IFC
  81. #endif
  82. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  83. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  84. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  85. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  86. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  87. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  88. | CSPR_V)
  89. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  90. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  91. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  92. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  93. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  94. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  95. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  96. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  97. #define CONFIG_SYS_NAND_ONFI_DETECTION
  98. /* ONFI NAND Flash mode0 Timing Params */
  99. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  100. FTIM0_NAND_TWP(0x18) | \
  101. FTIM0_NAND_TWCHT(0x07) | \
  102. FTIM0_NAND_TWH(0x0a))
  103. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  104. FTIM1_NAND_TWBE(0x39) | \
  105. FTIM1_NAND_TRR(0x0e) | \
  106. FTIM1_NAND_TRP(0x18))
  107. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  108. FTIM2_NAND_TREH(0x0a) | \
  109. FTIM2_NAND_TWHRE(0x1e))
  110. #define CONFIG_SYS_NAND_FTIM3 0x0
  111. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  112. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  113. #define CONFIG_MTD_NAND_VERIFY_WRITE
  114. #define CONFIG_CMD_NAND
  115. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  116. #ifndef SPL_NO_QIXIS
  117. #define CONFIG_FSL_QIXIS
  118. #endif
  119. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  120. #define QIXIS_BRDCFG4_OFFSET 0x54
  121. #define QIXIS_LBMAP_SWITCH 2
  122. #define QIXIS_QMAP_MASK 0xe0
  123. #define QIXIS_QMAP_SHIFT 5
  124. #define QIXIS_LBMAP_MASK 0x1f
  125. #define QIXIS_LBMAP_SHIFT 5
  126. #define QIXIS_LBMAP_DFLTBANK 0x00
  127. #define QIXIS_LBMAP_ALTBANK 0x20
  128. #define QIXIS_LBMAP_SD 0x00
  129. #define QIXIS_LBMAP_EMMC 0x00
  130. #define QIXIS_LBMAP_SD_QSPI 0x00
  131. #define QIXIS_LBMAP_QSPI 0x00
  132. #define QIXIS_RCW_SRC_SD 0x40
  133. #define QIXIS_RCW_SRC_EMMC 0x41
  134. #define QIXIS_RCW_SRC_QSPI 0x62
  135. #define QIXIS_RST_CTL_RESET 0x31
  136. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  137. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  138. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  139. #define QIXIS_RST_FORCE_MEM 0x01
  140. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  141. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  142. | CSPR_PORT_SIZE_8 \
  143. | CSPR_MSEL_GPCM \
  144. | CSPR_V)
  145. #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  146. | CSPR_PORT_SIZE_8 \
  147. | CSPR_MSEL_GPCM \
  148. | CSPR_V)
  149. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
  150. #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
  151. /* QIXIS Timing parameters*/
  152. #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  153. FTIM0_GPCM_TEADC(0x0e) | \
  154. FTIM0_GPCM_TEAHC(0x0e))
  155. #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  156. FTIM1_GPCM_TRAD(0x3f))
  157. #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  158. FTIM2_GPCM_TCH(0xf) | \
  159. FTIM2_GPCM_TWP(0x3E))
  160. #define SYS_FPGA_CS_FTIM3 0x0
  161. #if defined(CONFIG_TFABOOT) || \
  162. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  163. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  164. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  165. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  166. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  167. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  168. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  169. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  170. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  171. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
  172. #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
  173. #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
  174. #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
  175. #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
  176. #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
  177. #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
  178. #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
  179. #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
  180. #else
  181. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  182. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  183. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  184. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  185. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  186. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  187. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  188. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  189. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  190. #endif
  191. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  192. #define I2C_MUX_CH_VOL_MONITOR 0xA
  193. /* Voltage monitor on channel 2*/
  194. #define I2C_VOL_MONITOR_ADDR 0x63
  195. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  196. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  197. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  198. #define I2C_SVDD_MONITOR_ADDR 0x4F
  199. #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
  200. #define CONFIG_VID
  201. /* The lowest and highest voltage allowed for LS1088ARDB */
  202. #define VDD_MV_MIN 819
  203. #define VDD_MV_MAX 1212
  204. #define CONFIG_VOL_MONITOR_LTC3882_SET
  205. #define CONFIG_VOL_MONITOR_LTC3882_READ
  206. /* PM Bus commands code for LTC3882*/
  207. #define PMBUS_CMD_PAGE 0x0
  208. #define PMBUS_CMD_READ_VOUT 0x8B
  209. #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
  210. #define PMBUS_CMD_VOUT_COMMAND 0x21
  211. #define PWM_CHANNEL0 0x0
  212. /*
  213. * I2C bus multiplexer
  214. */
  215. #define I2C_MUX_PCA_ADDR_PRI 0x77
  216. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  217. #define I2C_RETIMER_ADDR 0x18
  218. #define I2C_MUX_CH_DEFAULT 0x8
  219. #define I2C_MUX_CH5 0xD
  220. #ifndef SPL_NO_RTC
  221. /*
  222. * RTC configuration
  223. */
  224. #define RTC
  225. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  226. #endif
  227. /* EEPROM */
  228. #define CONFIG_ID_EEPROM
  229. #define CONFIG_SYS_I2C_EEPROM_NXID
  230. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  231. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  232. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  233. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  234. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  235. #ifndef SPL_NO_QSPI
  236. /* QSPI device */
  237. #if defined(CONFIG_TFABOOT) || \
  238. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  239. #define FSL_QSPI_FLASH_SIZE (1 << 26)
  240. #define FSL_QSPI_FLASH_NUM 2
  241. #endif
  242. #endif
  243. #define CONFIG_CMD_MEMINFO
  244. #define CONFIG_SYS_MEMTEST_START 0x80000000
  245. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  246. #ifdef CONFIG_SPL_BUILD
  247. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  248. #else
  249. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  250. #endif
  251. #define CONFIG_FSL_MEMAC
  252. #ifndef SPL_NO_ENV
  253. /* Initial environment variables */
  254. #ifdef CONFIG_TFABOOT
  255. #define QSPI_MC_INIT_CMD \
  256. "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  257. "sf read 0x80100000 0xE00000 0x100000;" \
  258. "env exists secureboot && " \
  259. "sf read 0x80700000 0x700000 0x40000 && " \
  260. "sf read 0x80740000 0x740000 0x40000 && " \
  261. "esbc_validate 0x80700000 && " \
  262. "esbc_validate 0x80740000 ;" \
  263. "fsl_mc start mc 0x80000000 0x80100000\0"
  264. #define SD_MC_INIT_CMD \
  265. "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  266. "mmc read 0x80100000 0x7000 0x800;" \
  267. "env exists secureboot && " \
  268. "mmc read 0x80700000 0x3800 0x10 && " \
  269. "mmc read 0x80740000 0x3A00 0x10 && " \
  270. "esbc_validate 0x80700000 && " \
  271. "esbc_validate 0x80740000 ;" \
  272. "fsl_mc start mc 0x80000000 0x80100000\0"
  273. #else
  274. #if defined(CONFIG_QSPI_BOOT)
  275. #define MC_INIT_CMD \
  276. "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  277. "sf read 0x80100000 0xE00000 0x100000;" \
  278. "env exists secureboot && " \
  279. "sf read 0x80700000 0x700000 0x40000 && " \
  280. "sf read 0x80740000 0x740000 0x40000 && " \
  281. "esbc_validate 0x80700000 && " \
  282. "esbc_validate 0x80740000 ;" \
  283. "fsl_mc start mc 0x80000000 0x80100000\0" \
  284. "mcmemsize=0x70000000\0"
  285. #elif defined(CONFIG_SD_BOOT)
  286. #define MC_INIT_CMD \
  287. "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  288. "mmc read 0x80100000 0x7000 0x800;" \
  289. "env exists secureboot && " \
  290. "mmc read 0x80700000 0x3800 0x10 && " \
  291. "mmc read 0x80740000 0x3A00 0x10 && " \
  292. "esbc_validate 0x80700000 && " \
  293. "esbc_validate 0x80740000 ;" \
  294. "fsl_mc start mc 0x80000000 0x80100000\0" \
  295. "mcmemsize=0x70000000\0"
  296. #endif
  297. #endif /* CONFIG_TFABOOT */
  298. #undef CONFIG_EXTRA_ENV_SETTINGS
  299. #ifdef CONFIG_TFABOOT
  300. #define CONFIG_EXTRA_ENV_SETTINGS \
  301. "BOARD=ls1088ardb\0" \
  302. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  303. "ramdisk_addr=0x800000\0" \
  304. "ramdisk_size=0x2000000\0" \
  305. "fdt_high=0xa0000000\0" \
  306. "initrd_high=0xffffffffffffffff\0" \
  307. "fdt_addr=0x64f00000\0" \
  308. "kernel_addr=0x1000000\0" \
  309. "kernel_addr_sd=0x8000\0" \
  310. "kernelhdr_addr_sd=0x4000\0" \
  311. "kernel_start=0x580100000\0" \
  312. "kernelheader_start=0x580800000\0" \
  313. "scriptaddr=0x80000000\0" \
  314. "scripthdraddr=0x80080000\0" \
  315. "fdtheader_addr_r=0x80100000\0" \
  316. "kernelheader_addr=0x800000\0" \
  317. "kernelheader_addr_r=0x80200000\0" \
  318. "kernel_addr_r=0x81000000\0" \
  319. "kernelheader_size=0x40000\0" \
  320. "fdt_addr_r=0x90000000\0" \
  321. "load_addr=0xa0000000\0" \
  322. "kernel_size=0x2800000\0" \
  323. "kernel_size_sd=0x14000\0" \
  324. "kernelhdr_size_sd=0x10\0" \
  325. QSPI_MC_INIT_CMD \
  326. "mcmemsize=0x70000000\0" \
  327. BOOTENV \
  328. "boot_scripts=ls1088ardb_boot.scr\0" \
  329. "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
  330. "scan_dev_for_boot_part=" \
  331. "part list ${devtype} ${devnum} devplist; " \
  332. "env exists devplist || setenv devplist 1; " \
  333. "for distro_bootpart in ${devplist}; do " \
  334. "if fstype ${devtype} " \
  335. "${devnum}:${distro_bootpart} " \
  336. "bootfstype; then " \
  337. "run scan_dev_for_boot; " \
  338. "fi; " \
  339. "done\0" \
  340. "boot_a_script=" \
  341. "load ${devtype} ${devnum}:${distro_bootpart} " \
  342. "${scriptaddr} ${prefix}${script}; " \
  343. "env exists secureboot && load ${devtype} " \
  344. "${devnum}:${distro_bootpart} " \
  345. "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
  346. "env exists secureboot " \
  347. "&& esbc_validate ${scripthdraddr};" \
  348. "source ${scriptaddr}\0" \
  349. "installer=load mmc 0:2 $load_addr " \
  350. "/flex_installer_arm64.itb; " \
  351. "env exists mcinitcmd && run mcinitcmd && " \
  352. "mmc read 0x80001000 0x6800 0x800;" \
  353. "fsl_mc lazyapply dpl 0x80001000;" \
  354. "bootm $load_addr#ls1088ardb\0" \
  355. "qspi_bootcmd=echo Trying load from qspi..;" \
  356. "sf probe && sf read $load_addr " \
  357. "$kernel_addr $kernel_size ; env exists secureboot " \
  358. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  359. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  360. "bootm $load_addr#$BOARD\0" \
  361. "sd_bootcmd=echo Trying load from sd card..;" \
  362. "mmcinfo; mmc read $load_addr " \
  363. "$kernel_addr_sd $kernel_size_sd ;" \
  364. "env exists secureboot && mmc read $kernelheader_addr_r "\
  365. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  366. " && esbc_validate ${kernelheader_addr_r};" \
  367. "bootm $load_addr#$BOARD\0"
  368. #else
  369. #define CONFIG_EXTRA_ENV_SETTINGS \
  370. "BOARD=ls1088ardb\0" \
  371. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  372. "ramdisk_addr=0x800000\0" \
  373. "ramdisk_size=0x2000000\0" \
  374. "fdt_high=0xa0000000\0" \
  375. "initrd_high=0xffffffffffffffff\0" \
  376. "fdt_addr=0x64f00000\0" \
  377. "kernel_addr=0x1000000\0" \
  378. "kernel_addr_sd=0x8000\0" \
  379. "kernelhdr_addr_sd=0x4000\0" \
  380. "kernel_start=0x580100000\0" \
  381. "kernelheader_start=0x580800000\0" \
  382. "scriptaddr=0x80000000\0" \
  383. "scripthdraddr=0x80080000\0" \
  384. "fdtheader_addr_r=0x80100000\0" \
  385. "kernelheader_addr=0x800000\0" \
  386. "kernelheader_addr_r=0x80200000\0" \
  387. "kernel_addr_r=0x81000000\0" \
  388. "kernelheader_size=0x40000\0" \
  389. "fdt_addr_r=0x90000000\0" \
  390. "load_addr=0xa0000000\0" \
  391. "kernel_size=0x2800000\0" \
  392. "kernel_size_sd=0x14000\0" \
  393. "kernelhdr_size_sd=0x10\0" \
  394. MC_INIT_CMD \
  395. BOOTENV \
  396. "boot_scripts=ls1088ardb_boot.scr\0" \
  397. "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
  398. "scan_dev_for_boot_part=" \
  399. "part list ${devtype} ${devnum} devplist; " \
  400. "env exists devplist || setenv devplist 1; " \
  401. "for distro_bootpart in ${devplist}; do " \
  402. "if fstype ${devtype} " \
  403. "${devnum}:${distro_bootpart} " \
  404. "bootfstype; then " \
  405. "run scan_dev_for_boot; " \
  406. "fi; " \
  407. "done\0" \
  408. "boot_a_script=" \
  409. "load ${devtype} ${devnum}:${distro_bootpart} " \
  410. "${scriptaddr} ${prefix}${script}; " \
  411. "env exists secureboot && load ${devtype} " \
  412. "${devnum}:${distro_bootpart} " \
  413. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  414. "&& esbc_validate ${scripthdraddr};" \
  415. "source ${scriptaddr}\0" \
  416. "installer=load mmc 0:2 $load_addr " \
  417. "/flex_installer_arm64.itb; " \
  418. "env exists mcinitcmd && run mcinitcmd && " \
  419. "mmc read 0x80001000 0x6800 0x800;" \
  420. "fsl_mc lazyapply dpl 0x80001000;" \
  421. "bootm $load_addr#ls1088ardb\0" \
  422. "qspi_bootcmd=echo Trying load from qspi..;" \
  423. "sf probe && sf read $load_addr " \
  424. "$kernel_addr $kernel_size ; env exists secureboot " \
  425. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  426. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  427. "bootm $load_addr#$BOARD\0" \
  428. "sd_bootcmd=echo Trying load from sd card..;" \
  429. "mmcinfo; mmc read $load_addr " \
  430. "$kernel_addr_sd $kernel_size_sd ;" \
  431. "env exists secureboot && mmc read $kernelheader_addr_r "\
  432. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  433. " && esbc_validate ${kernelheader_addr_r};" \
  434. "bootm $load_addr#$BOARD\0"
  435. #endif /* CONFIG_TFABOOT */
  436. #undef CONFIG_BOOTCOMMAND
  437. #ifdef CONFIG_TFABOOT
  438. #define QSPI_NOR_BOOTCOMMAND \
  439. "sf read 0x80001000 0xd00000 0x100000;" \
  440. "env exists mcinitcmd && env exists secureboot " \
  441. " && sf read 0x80780000 0x780000 0x100000 " \
  442. "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  443. "&& fsl_mc lazyapply dpl 0x80001000;" \
  444. "run distro_bootcmd;run qspi_bootcmd;" \
  445. "env exists secureboot && esbc_halt;"
  446. #define SD_BOOTCOMMAND \
  447. "env exists mcinitcmd && mmcinfo; " \
  448. "mmc read 0x80001000 0x6800 0x800; " \
  449. "env exists mcinitcmd && env exists secureboot " \
  450. " && mmc read 0x80780000 0x3C00 0x10 " \
  451. "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  452. "&& fsl_mc lazyapply dpl 0x80001000;" \
  453. "run distro_bootcmd;run sd_bootcmd;" \
  454. "env exists secureboot && esbc_halt;"
  455. #else
  456. #if defined(CONFIG_QSPI_BOOT)
  457. /* Try to boot an on-QSPI kernel first, then do normal distro boot */
  458. #define CONFIG_BOOTCOMMAND \
  459. "sf read 0x80001000 0xd00000 0x100000;" \
  460. "env exists mcinitcmd && env exists secureboot " \
  461. " && sf read 0x80780000 0x780000 0x100000 " \
  462. "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  463. "&& fsl_mc lazyapply dpl 0x80001000;" \
  464. "run distro_bootcmd;run qspi_bootcmd;" \
  465. "env exists secureboot && esbc_halt;"
  466. /* Try to boot an on-SD kernel first, then do normal distro boot */
  467. #elif defined(CONFIG_SD_BOOT)
  468. #define CONFIG_BOOTCOMMAND \
  469. "env exists mcinitcmd && mmcinfo; " \
  470. "mmc read 0x80001000 0x6800 0x800; " \
  471. "env exists mcinitcmd && env exists secureboot " \
  472. " && mmc read 0x80780000 0x3C00 0x10 " \
  473. "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  474. "&& fsl_mc lazyapply dpl 0x80001000;" \
  475. "run distro_bootcmd;run sd_bootcmd;" \
  476. "env exists secureboot && esbc_halt;"
  477. #endif
  478. #endif /* CONFIG_TFABOOT */
  479. /* MAC/PHY configuration */
  480. #ifdef CONFIG_FSL_MC_ENET
  481. #define CONFIG_PHYLIB
  482. #define CONFIG_PHY_VITESSE
  483. #define AQ_PHY_ADDR1 0x00
  484. #define AQR105_IRQ_MASK 0x00000004
  485. #define QSGMII1_PORT1_PHY_ADDR 0x0c
  486. #define QSGMII1_PORT2_PHY_ADDR 0x0d
  487. #define QSGMII1_PORT3_PHY_ADDR 0x0e
  488. #define QSGMII1_PORT4_PHY_ADDR 0x0f
  489. #define QSGMII2_PORT1_PHY_ADDR 0x1c
  490. #define QSGMII2_PORT2_PHY_ADDR 0x1d
  491. #define QSGMII2_PORT3_PHY_ADDR 0x1e
  492. #define QSGMII2_PORT4_PHY_ADDR 0x1f
  493. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  494. #define CONFIG_PHY_GIGE
  495. #endif
  496. #endif
  497. /* MMC */
  498. #ifdef CONFIG_MMC
  499. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  500. #endif
  501. #ifndef SPL_NO_ENV
  502. #define BOOT_TARGET_DEVICES(func) \
  503. func(MMC, mmc, 0) \
  504. func(SCSI, scsi, 0) \
  505. func(DHCP, dhcp, na)
  506. #include <config_distro_bootcmd.h>
  507. #endif
  508. #include <asm/fsl_secure_boot.h>
  509. #endif /* __LS1088A_RDB_H */