ls1088aqds.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #ifndef __LS1088A_QDS_H
  6. #define __LS1088A_QDS_H
  7. #include "ls1088a_common.h"
  8. #ifndef __ASSEMBLY__
  9. unsigned long get_board_sys_clk(void);
  10. unsigned long get_board_ddr_clk(void);
  11. #endif
  12. #ifdef CONFIG_TFABOOT
  13. #define CONFIG_SYS_MMC_ENV_DEV 0
  14. #define CONFIG_MISC_INIT_R
  15. #else
  16. #if defined(CONFIG_QSPI_BOOT)
  17. #elif defined(CONFIG_SD_BOOT)
  18. #define CONFIG_SYS_MMC_ENV_DEV 0
  19. #endif
  20. #endif
  21. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  22. #define CONFIG_QIXIS_I2C_ACCESS
  23. #define SYS_NO_FLASH
  24. #undef CONFIG_CMD_IMLS
  25. #define CONFIG_SYS_CLK_FREQ 100000000
  26. #define CONFIG_DDR_CLK_FREQ 100000000
  27. #else
  28. #define CONFIG_QIXIS_I2C_ACCESS
  29. #ifndef CONFIG_DM_I2C
  30. #define CONFIG_SYS_I2C_EARLY_INIT
  31. #endif
  32. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  33. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  34. #endif
  35. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  36. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  37. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  38. #define CONFIG_DDR_SPD
  39. #define CONFIG_DDR_ECC
  40. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  41. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  42. #define SPD_EEPROM_ADDRESS 0x51
  43. #define CONFIG_SYS_SPD_BUS_NUM 0
  44. /*
  45. * IFC Definitions
  46. */
  47. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  48. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  49. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  50. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  51. #define CONFIG_SYS_NOR0_CSPR \
  52. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  53. CSPR_PORT_SIZE_16 | \
  54. CSPR_MSEL_NOR | \
  55. CSPR_V)
  56. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  57. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  58. CSPR_PORT_SIZE_16 | \
  59. CSPR_MSEL_NOR | \
  60. CSPR_V)
  61. #define CONFIG_SYS_NOR1_CSPR \
  62. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
  63. CSPR_PORT_SIZE_16 | \
  64. CSPR_MSEL_NOR | \
  65. CSPR_V)
  66. #define CONFIG_SYS_NOR1_CSPR_EARLY \
  67. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  68. CSPR_PORT_SIZE_16 | \
  69. CSPR_MSEL_NOR | \
  70. CSPR_V)
  71. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  72. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  73. FTIM0_NOR_TEADC(0x5) | \
  74. FTIM0_NOR_TAVDS(0x6) | \
  75. FTIM0_NOR_TEAHC(0x5))
  76. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  77. FTIM1_NOR_TRAD_NOR(0x1a) | \
  78. FTIM1_NOR_TSEQRAD_NOR(0x13))
  79. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
  80. FTIM2_NOR_TCH(0x8) | \
  81. FTIM2_NOR_TWPH(0xe) | \
  82. FTIM2_NOR_TWP(0x1c))
  83. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  84. #define CONFIG_SYS_IFC_CCR 0x01000000
  85. #ifndef SYS_NO_FLASH
  86. #define CONFIG_SYS_FLASH_QUIET_TEST
  87. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  88. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  89. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  90. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  91. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  92. #define CONFIG_SYS_FLASH_EMPTY_INFO
  93. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  94. CONFIG_SYS_FLASH_BASE + 0x40000000}
  95. #endif
  96. #endif
  97. #define CONFIG_NAND_FSL_IFC
  98. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  99. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  100. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  101. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  102. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  103. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  104. | CSPR_V)
  105. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  106. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  107. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  108. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  109. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  110. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  111. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  112. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  113. #define CONFIG_SYS_NAND_ONFI_DETECTION
  114. /* ONFI NAND Flash mode0 Timing Params */
  115. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  116. FTIM0_NAND_TWP(0x18) | \
  117. FTIM0_NAND_TWCHT(0x07) | \
  118. FTIM0_NAND_TWH(0x0a))
  119. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  120. FTIM1_NAND_TWBE(0x39) | \
  121. FTIM1_NAND_TRR(0x0e) | \
  122. FTIM1_NAND_TRP(0x18))
  123. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  124. FTIM2_NAND_TREH(0x0a) | \
  125. FTIM2_NAND_TWHRE(0x1e))
  126. #define CONFIG_SYS_NAND_FTIM3 0x0
  127. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  128. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  129. #define CONFIG_MTD_NAND_VERIFY_WRITE
  130. #define CONFIG_CMD_NAND
  131. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  132. #define CONFIG_FSL_QIXIS
  133. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  134. #define QIXIS_LBMAP_SWITCH 6
  135. #define QIXIS_QMAP_MASK 0xe0
  136. #define QIXIS_QMAP_SHIFT 5
  137. #define QIXIS_LBMAP_MASK 0x0f
  138. #define QIXIS_LBMAP_SHIFT 0
  139. #define QIXIS_LBMAP_DFLTBANK 0x0e
  140. #define QIXIS_LBMAP_ALTBANK 0x2e
  141. #define QIXIS_LBMAP_SD 0x00
  142. #define QIXIS_LBMAP_EMMC 0x00
  143. #define QIXIS_LBMAP_IFC 0x00
  144. #define QIXIS_LBMAP_SD_QSPI 0x0e
  145. #define QIXIS_LBMAP_QSPI 0x0e
  146. #define QIXIS_RCW_SRC_IFC 0x25
  147. #define QIXIS_RCW_SRC_SD 0x40
  148. #define QIXIS_RCW_SRC_EMMC 0x41
  149. #define QIXIS_RCW_SRC_QSPI 0x62
  150. #define QIXIS_RST_CTL_RESET 0x41
  151. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  152. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  153. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  154. #define QIXIS_RST_FORCE_MEM 0x01
  155. #define QIXIS_STAT_PRES1 0xb
  156. #define QIXIS_SDID_MASK 0x07
  157. #define QIXIS_ESDHC_NO_ADAPTER 0x7
  158. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  159. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  160. | CSPR_PORT_SIZE_8 \
  161. | CSPR_MSEL_GPCM \
  162. | CSPR_V)
  163. #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  164. | CSPR_PORT_SIZE_8 \
  165. | CSPR_MSEL_GPCM \
  166. | CSPR_V)
  167. #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  168. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  169. #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
  170. #else
  171. #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
  172. #endif
  173. /* QIXIS Timing parameters*/
  174. #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  175. FTIM0_GPCM_TEADC(0x0e) | \
  176. FTIM0_GPCM_TEAHC(0x0e))
  177. #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  178. FTIM1_GPCM_TRAD(0x3f))
  179. #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  180. FTIM2_GPCM_TCH(0xf) | \
  181. FTIM2_GPCM_TWP(0x3E))
  182. #define SYS_FPGA_CS_FTIM3 0x0
  183. #ifdef CONFIG_TFABOOT
  184. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  185. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  186. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  187. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  188. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  189. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  190. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  191. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  192. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  193. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  194. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  195. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  196. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  197. #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  198. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  199. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  200. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  201. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  202. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  203. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  204. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  205. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  206. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  207. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  208. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  209. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  210. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  211. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  212. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  213. #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
  214. #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
  215. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  216. #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
  217. #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
  218. #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
  219. #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
  220. #else
  221. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  222. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  223. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  224. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  225. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  226. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  227. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  228. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  229. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  230. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
  231. #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
  232. #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
  233. #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
  234. #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
  235. #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
  236. #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
  237. #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
  238. #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
  239. #else
  240. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  241. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  242. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  243. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  244. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  245. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  246. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  247. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  248. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  249. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  250. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  251. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  252. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  253. #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  254. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  255. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  256. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  257. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  258. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  259. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  260. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  261. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  262. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  263. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  264. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  265. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  266. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  267. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  268. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  269. #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
  270. #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
  271. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  272. #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
  273. #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
  274. #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
  275. #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
  276. #endif
  277. #endif
  278. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  279. /*
  280. * I2C bus multiplexer
  281. */
  282. #define I2C_MUX_PCA_ADDR_PRI 0x77
  283. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  284. #define I2C_RETIMER_ADDR 0x18
  285. #define I2C_RETIMER_ADDR2 0x19
  286. #define I2C_MUX_CH_DEFAULT 0x8
  287. #define I2C_MUX_CH5 0xD
  288. #define I2C_MUX_CH_VOL_MONITOR 0xA
  289. /* Voltage monitor on channel 2*/
  290. #define I2C_VOL_MONITOR_ADDR 0x63
  291. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  292. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  293. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  294. #define I2C_SVDD_MONITOR_ADDR 0x4F
  295. #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
  296. #define CONFIG_VID
  297. /* The lowest and highest voltage allowed for LS1088AQDS */
  298. #define VDD_MV_MIN 819
  299. #define VDD_MV_MAX 1212
  300. #define CONFIG_VOL_MONITOR_LTC3882_SET
  301. #define CONFIG_VOL_MONITOR_LTC3882_READ
  302. /* PM Bus commands code for LTC3882*/
  303. #define PMBUS_CMD_PAGE 0x0
  304. #define PMBUS_CMD_READ_VOUT 0x8B
  305. #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
  306. #define PMBUS_CMD_VOUT_COMMAND 0x21
  307. #define PWM_CHANNEL0 0x0
  308. /*
  309. * RTC configuration
  310. */
  311. #define RTC
  312. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  313. /* EEPROM */
  314. #define CONFIG_ID_EEPROM
  315. #define CONFIG_SYS_I2C_EEPROM_NXID
  316. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  317. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  318. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  319. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  320. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  321. /* QSPI device */
  322. #if defined(CONFIG_TFABOOT) || \
  323. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  324. #define FSL_QSPI_FLASH_SIZE (1 << 26)
  325. #define FSL_QSPI_FLASH_NUM 2
  326. #endif
  327. #ifdef CONFIG_FSL_DSPI
  328. #define CONFIG_SPI_FLASH_STMICRO
  329. #define CONFIG_SPI_FLASH_SST
  330. #define CONFIG_SPI_FLASH_EON
  331. #if !defined(CONFIG_TFABOOT) && \
  332. !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  333. #endif
  334. #endif
  335. #define CONFIG_CMD_MEMINFO
  336. #define CONFIG_SYS_MEMTEST_START 0x80000000
  337. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  338. #ifdef CONFIG_SPL_BUILD
  339. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  340. #else
  341. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  342. #endif
  343. #define CONFIG_FSL_MEMAC
  344. /* MMC */
  345. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  346. #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
  347. QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
  348. /* Initial environment variables */
  349. #ifdef CONFIG_NXP_ESBC
  350. #undef CONFIG_EXTRA_ENV_SETTINGS
  351. #define CONFIG_EXTRA_ENV_SETTINGS \
  352. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  353. "loadaddr=0x90100000\0" \
  354. "kernel_addr=0x100000\0" \
  355. "ramdisk_addr=0x800000\0" \
  356. "ramdisk_size=0x2000000\0" \
  357. "fdt_high=0xa0000000\0" \
  358. "initrd_high=0xffffffffffffffff\0" \
  359. "kernel_start=0x1000000\0" \
  360. "kernel_load=0xa0000000\0" \
  361. "kernel_size=0x2800000\0" \
  362. "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
  363. "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
  364. "sf read 0xa0e00000 0xe00000 0x100000;" \
  365. "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
  366. "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
  367. "mcmemsize=0x70000000 \0"
  368. #else /* if !(CONFIG_NXP_ESBC) */
  369. #ifdef CONFIG_TFABOOT
  370. #define QSPI_MC_INIT_CMD \
  371. "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  372. "sf read 0x80100000 0xE00000 0x100000;" \
  373. "fsl_mc start mc 0x80000000 0x80100000\0"
  374. #define SD_MC_INIT_CMD \
  375. "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  376. "mmc read 0x80100000 0x7000 0x800;" \
  377. "fsl_mc start mc 0x80000000 0x80100000\0"
  378. #define IFC_MC_INIT_CMD \
  379. "fsl_mc start mc 0x580A00000 0x580E00000\0"
  380. #undef CONFIG_EXTRA_ENV_SETTINGS
  381. #define CONFIG_EXTRA_ENV_SETTINGS \
  382. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  383. "loadaddr=0x90100000\0" \
  384. "kernel_addr=0x100000\0" \
  385. "kernel_addr_sd=0x800\0" \
  386. "ramdisk_addr=0x800000\0" \
  387. "ramdisk_size=0x2000000\0" \
  388. "fdt_high=0xa0000000\0" \
  389. "initrd_high=0xffffffffffffffff\0" \
  390. "kernel_start=0x1000000\0" \
  391. "kernel_start_sd=0x8000\0" \
  392. "kernel_load=0xa0000000\0" \
  393. "kernel_size=0x2800000\0" \
  394. "kernel_size_sd=0x14000\0" \
  395. "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  396. "sf read 0x80100000 0xE00000 0x100000;" \
  397. "fsl_mc start mc 0x80000000 0x80100000\0" \
  398. "mcmemsize=0x70000000 \0"
  399. #define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \
  400. "sf read 0x80001000 0xd00000 0x100000;"\
  401. " fsl_mc lazyapply dpl 0x80001000 &&" \
  402. " sf read $kernel_load $kernel_start" \
  403. " $kernel_size && bootm $kernel_load"
  404. #define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
  405. " fsl_mc lazyapply dpl 0x80001000 &&" \
  406. " mmc read $kernel_load $kernel_start_sd" \
  407. " $kernel_size_sd && bootm $kernel_load"
  408. #define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
  409. " cp.b $kernel_start $kernel_load" \
  410. " $kernel_size && bootm $kernel_load"
  411. #else
  412. #if defined(CONFIG_QSPI_BOOT)
  413. #undef CONFIG_EXTRA_ENV_SETTINGS
  414. #define CONFIG_EXTRA_ENV_SETTINGS \
  415. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  416. "loadaddr=0x90100000\0" \
  417. "kernel_addr=0x100000\0" \
  418. "ramdisk_addr=0x800000\0" \
  419. "ramdisk_size=0x2000000\0" \
  420. "fdt_high=0xa0000000\0" \
  421. "initrd_high=0xffffffffffffffff\0" \
  422. "kernel_start=0x1000000\0" \
  423. "kernel_load=0xa0000000\0" \
  424. "kernel_size=0x2800000\0" \
  425. "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  426. "sf read 0x80100000 0xE00000 0x100000;" \
  427. "fsl_mc start mc 0x80000000 0x80100000\0" \
  428. "mcmemsize=0x70000000 \0"
  429. #elif defined(CONFIG_SD_BOOT)
  430. #undef CONFIG_EXTRA_ENV_SETTINGS
  431. #define CONFIG_EXTRA_ENV_SETTINGS \
  432. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  433. "loadaddr=0x90100000\0" \
  434. "kernel_addr=0x800\0" \
  435. "ramdisk_addr=0x800000\0" \
  436. "ramdisk_size=0x2000000\0" \
  437. "fdt_high=0xa0000000\0" \
  438. "initrd_high=0xffffffffffffffff\0" \
  439. "kernel_start=0x8000\0" \
  440. "kernel_load=0xa0000000\0" \
  441. "kernel_size=0x14000\0" \
  442. "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  443. "mmc read 0x80100000 0x7000 0x800;" \
  444. "fsl_mc start mc 0x80000000 0x80100000\0" \
  445. "mcmemsize=0x70000000 \0"
  446. #else /* NOR BOOT */
  447. #undef CONFIG_EXTRA_ENV_SETTINGS
  448. #define CONFIG_EXTRA_ENV_SETTINGS \
  449. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  450. "loadaddr=0x90100000\0" \
  451. "kernel_addr=0x100000\0" \
  452. "ramdisk_addr=0x800000\0" \
  453. "ramdisk_size=0x2000000\0" \
  454. "fdt_high=0xa0000000\0" \
  455. "initrd_high=0xffffffffffffffff\0" \
  456. "kernel_start=0x1000000\0" \
  457. "kernel_load=0xa0000000\0" \
  458. "kernel_size=0x2800000\0" \
  459. "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
  460. "mcmemsize=0x70000000 \0"
  461. #endif
  462. #endif /* CONFIG_TFABOOT */
  463. #endif /* CONFIG_NXP_ESBC */
  464. #ifdef CONFIG_FSL_MC_ENET
  465. #define CONFIG_FSL_MEMAC
  466. #define CONFIG_PHYLIB
  467. #define CONFIG_PHYLIB_10G
  468. #define CONFIG_PHY_VITESSE
  469. #define CONFIG_PHY_REALTEK
  470. #define CONFIG_PHY_TERANETICS
  471. #define RGMII_PHY1_ADDR 0x1
  472. #define RGMII_PHY2_ADDR 0x2
  473. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  474. #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
  475. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  476. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  477. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  478. #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  479. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  480. #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  481. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  482. #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  483. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  484. #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  485. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  486. #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  487. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  488. #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  489. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  490. #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  491. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  492. #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  493. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  494. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  495. #endif
  496. #define BOOT_TARGET_DEVICES(func) \
  497. func(USB, usb, 0) \
  498. func(MMC, mmc, 0) \
  499. func(SCSI, scsi, 0) \
  500. func(DHCP, dhcp, na)
  501. #include <config_distro_bootcmd.h>
  502. #include <asm/fsl_secure_boot.h>
  503. #endif /* __LS1088A_QDS_H */