ls1088a_common.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #ifndef __LS1088_COMMON_H
  6. #define __LS1088_COMMON_H
  7. /* SPL build */
  8. #ifdef CONFIG_SPL_BUILD
  9. #define SPL_NO_BOARDINFO
  10. #define SPL_NO_QIXIS
  11. #define SPL_NO_PCI
  12. #define SPL_NO_ENV
  13. #define SPL_NO_RTC
  14. #define SPL_NO_USB
  15. #define SPL_NO_SATA
  16. #define SPL_NO_QSPI
  17. #define SPL_NO_IFC
  18. #undef CONFIG_DISPLAY_CPUINFO
  19. #endif
  20. #define CONFIG_REMAKE_ELF
  21. #include <asm/arch/stream_id_lsch3.h>
  22. #include <asm/arch/config.h>
  23. #include <asm/arch/soc.h>
  24. #define LS1088ARDB_PB_BOARD 0x4A
  25. /* Link Definitions */
  26. #ifdef CONFIG_TFABOOT
  27. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  28. #else
  29. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  30. #endif
  31. /* Link Definitions */
  32. #ifdef CONFIG_TFABOOT
  33. #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  34. #else
  35. #ifdef CONFIG_QSPI_BOOT
  36. #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  37. #endif
  38. #endif
  39. #define CONFIG_SKIP_LOWLEVEL_INIT
  40. #define CONFIG_VERY_BIG_RAM
  41. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  42. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  43. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  44. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
  45. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
  46. /*
  47. * SMP Definitinos
  48. */
  49. #define CPU_RELEASE_ADDR secondary_boot_func
  50. #ifdef CONFIG_PCI
  51. #define CONFIG_CMD_PCI
  52. #endif
  53. /* Size of malloc() pool */
  54. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  55. /* I2C */
  56. #ifndef CONFIG_DM_I2C
  57. #define CONFIG_SYS_I2C
  58. #endif
  59. /* Serial Port */
  60. #define CONFIG_SYS_NS16550_SERIAL
  61. #define CONFIG_SYS_NS16550_REG_SIZE 1
  62. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  63. #define CONFIG_BAUDRATE 115200
  64. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  65. #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
  66. /* IFC */
  67. #define CONFIG_FSL_IFC
  68. #endif
  69. /*
  70. * During booting, IFC is mapped at the region of 0x30000000.
  71. * But this region is limited to 256MB. To accommodate NOR, promjet
  72. * and FPGA. This region is divided as below:
  73. * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  74. * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  75. * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  76. *
  77. * To accommodate bigger NOR flash and other devices, we will map IFC
  78. * chip selects to as below:
  79. * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  80. * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  81. * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  82. * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  83. * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  84. *
  85. * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  86. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  87. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  88. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  89. * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  90. */
  91. #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
  92. #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
  93. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  94. #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
  95. #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
  96. #ifndef __ASSEMBLY__
  97. unsigned long long get_qixis_addr(void);
  98. #endif
  99. #define QIXIS_BASE get_qixis_addr()
  100. #define QIXIS_BASE_PHYS 0x20000000
  101. #define QIXIS_BASE_PHYS_EARLY 0xC000000
  102. #define CONFIG_SYS_NAND_BASE 0x530000000ULL
  103. #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
  104. /* MC firmware */
  105. /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
  106. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  107. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  108. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  109. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  110. #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
  111. #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
  112. /* Define phy_reset function to boot the MC based on mcinitcmd.
  113. * This happens late enough to properly fixup u-boot env MAC addresses.
  114. */
  115. #define CONFIG_RESET_PHY_R
  116. /*
  117. * Carve out a DDR region which will not be used by u-boot/Linux
  118. *
  119. * It will be used by MC and Debug Server. The MC region must be
  120. * 512MB aligned, so the min size to hide is 512MB.
  121. */
  122. #if defined(CONFIG_FSL_MC_ENET)
  123. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
  124. #endif
  125. /* Command line configuration */
  126. #define CONFIG_CMD_CACHE
  127. /* Miscellaneous configurable options */
  128. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  129. /* SATA */
  130. #ifdef CONFIG_SCSI
  131. #define CONFIG_SCSI_AHCI_PLAT
  132. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  133. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  134. #define CONFIG_SYS_SCSI_MAX_LUN 1
  135. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  136. CONFIG_SYS_SCSI_MAX_LUN)
  137. #endif
  138. /* Physical Memory Map */
  139. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  140. #define CONFIG_HWCONFIG
  141. #define HWCONFIG_BUFFER_SIZE 128
  142. /* #define CONFIG_DISPLAY_CPUINFO */
  143. #ifndef SPL_NO_ENV
  144. /* Allow to overwrite serial and ethaddr */
  145. #define CONFIG_ENV_OVERWRITE
  146. /* Initial environment variables */
  147. #define CONFIG_EXTRA_ENV_SETTINGS \
  148. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  149. "loadaddr=0x80100000\0" \
  150. "kernel_addr=0x100000\0" \
  151. "ramdisk_addr=0x800000\0" \
  152. "ramdisk_size=0x2000000\0" \
  153. "fdt_high=0xa0000000\0" \
  154. "initrd_high=0xffffffffffffffff\0" \
  155. "kernel_start=0x581000000\0" \
  156. "kernel_load=0xa0000000\0" \
  157. "kernel_size=0x2800000\0" \
  158. "console=ttyAMA0,38400n8\0" \
  159. "mcinitcmd=fsl_mc start mc 0x580a00000" \
  160. " 0x580e00000 \0"
  161. #ifndef CONFIG_TFABOOT
  162. #if defined(CONFIG_QSPI_BOOT)
  163. #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
  164. "sf read 0x80001000 0xd00000 0x100000;"\
  165. " fsl_mc lazyapply dpl 0x80001000 &&" \
  166. " sf read $kernel_load $kernel_start" \
  167. " $kernel_size && bootm $kernel_load"
  168. #elif defined(CONFIG_SD_BOOT)
  169. #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
  170. " fsl_mc lazyapply dpl 0x80001000 &&" \
  171. " mmc read $kernel_load $kernel_start" \
  172. " $kernel_size && bootm $kernel_load"
  173. #else /* NOR BOOT*/
  174. #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
  175. " cp.b $kernel_start $kernel_load" \
  176. " $kernel_size && bootm $kernel_load"
  177. #endif
  178. #endif /* CONFIG_TFABOOT */
  179. #endif
  180. /* Monitor Command Prompt */
  181. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  182. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  183. sizeof(CONFIG_SYS_PROMPT) + 16)
  184. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  185. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  186. #ifdef CONFIG_SPL
  187. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  188. #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
  189. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  190. #define CONFIG_SPL_MAX_SIZE 0x16000
  191. #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
  192. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  193. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
  194. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  195. #ifdef CONFIG_NXP_ESBC
  196. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  197. /*
  198. * HDR would be appended at end of image and copied to DDR along
  199. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  200. * size increases then increase this size in case of secure boot as
  201. * it uses raw u-boot image instead of fit image.
  202. */
  203. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  204. #else
  205. #define CONFIG_SYS_MONITOR_LEN 0x100000
  206. #endif /* ifdef CONFIG_NXP_ESBC */
  207. #endif
  208. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  209. #endif /* __LS1088_COMMON_H */