ls1046ardb.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __LS1046ARDB_H__
  7. #define __LS1046ARDB_H__
  8. #include "ls1046a_common.h"
  9. #define CONFIG_SYS_CLK_FREQ 100000000
  10. #define CONFIG_DDR_CLK_FREQ 100000000
  11. #define CONFIG_LAYERSCAPE_NS_ACCESS
  12. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  13. /* Physical Memory Map */
  14. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  15. #define CONFIG_DDR_SPD
  16. #define SPD_EEPROM_ADDRESS 0x51
  17. #define CONFIG_SYS_SPD_BUS_NUM 0
  18. #define CONFIG_DDR_ECC
  19. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  20. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  21. #ifdef CONFIG_SD_BOOT
  22. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
  23. #ifdef CONFIG_EMMC_BOOT
  24. #define CONFIG_SYS_FSL_PBL_RCW \
  25. board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
  26. #else
  27. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
  28. #endif
  29. #elif defined(CONFIG_QSPI_BOOT)
  30. #define CONFIG_SYS_FSL_PBL_RCW \
  31. board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
  32. #define CONFIG_SYS_FSL_PBL_PBI \
  33. board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
  34. #define CONFIG_SYS_UBOOT_BASE 0x40100000
  35. #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
  36. #endif
  37. #ifndef SPL_NO_IFC
  38. /* IFC */
  39. #define CONFIG_FSL_IFC
  40. /*
  41. * NAND Flash Definitions
  42. */
  43. #define CONFIG_NAND_FSL_IFC
  44. #endif
  45. #define CONFIG_SYS_NAND_BASE 0x7e800000
  46. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  47. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  48. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  49. | CSPR_PORT_SIZE_8 \
  50. | CSPR_MSEL_NAND \
  51. | CSPR_V)
  52. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  53. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  54. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  55. | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
  56. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  57. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  58. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  59. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  60. #define CONFIG_SYS_NAND_ONFI_DETECTION
  61. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  62. FTIM0_NAND_TWP(0x18) | \
  63. FTIM0_NAND_TWCHT(0x7) | \
  64. FTIM0_NAND_TWH(0xa))
  65. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  66. FTIM1_NAND_TWBE(0x39) | \
  67. FTIM1_NAND_TRR(0xe) | \
  68. FTIM1_NAND_TRP(0x18))
  69. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  70. FTIM2_NAND_TREH(0xa) | \
  71. FTIM2_NAND_TWHRE(0x1e))
  72. #define CONFIG_SYS_NAND_FTIM3 0x0
  73. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  74. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  75. #define CONFIG_MTD_NAND_VERIFY_WRITE
  76. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  77. /*
  78. * CPLD
  79. */
  80. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  81. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  82. #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
  83. #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  84. CSPR_PORT_SIZE_8 | \
  85. CSPR_MSEL_GPCM | \
  86. CSPR_V)
  87. #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
  88. #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
  89. /* CPLD Timing parameters for IFC GPCM */
  90. #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  91. FTIM0_GPCM_TEADC(0x0e) | \
  92. FTIM0_GPCM_TEAHC(0x0e))
  93. #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  94. FTIM1_GPCM_TRAD(0x3f))
  95. #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  96. FTIM2_GPCM_TCH(0xf) | \
  97. FTIM2_GPCM_TWP(0x3E))
  98. #define CONFIG_SYS_CPLD_FTIM3 0x0
  99. /* IFC Timing Params */
  100. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  101. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  102. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  103. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  104. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  105. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  106. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  107. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  108. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
  109. #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
  110. #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
  111. #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
  112. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
  113. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
  114. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
  115. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
  116. /* EEPROM */
  117. #define CONFIG_ID_EEPROM
  118. #define CONFIG_SYS_I2C_EEPROM_NXID
  119. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  120. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  121. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  122. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  123. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  124. #define I2C_RETIMER_ADDR 0x18
  125. /* PMIC */
  126. #define CONFIG_POWER
  127. #ifdef CONFIG_POWER
  128. #define CONFIG_POWER_I2C
  129. #endif
  130. /*
  131. * Environment
  132. */
  133. #ifndef SPL_NO_ENV
  134. #define CONFIG_ENV_OVERWRITE
  135. #endif
  136. #ifdef CONFIG_TFABOOT
  137. #define CONFIG_SYS_MMC_ENV_DEV 0
  138. #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
  139. #else
  140. #if defined(CONFIG_SD_BOOT)
  141. #define CONFIG_SYS_MMC_ENV_DEV 0
  142. #endif
  143. #endif
  144. #define AQR105_IRQ_MASK 0x80000000
  145. /* FMan */
  146. #ifndef SPL_NO_FMAN
  147. #ifdef CONFIG_NET
  148. #define CONFIG_PHY_REALTEK
  149. #endif
  150. #ifdef CONFIG_SYS_DPAA_FMAN
  151. #define RGMII_PHY1_ADDR 0x1
  152. #define RGMII_PHY2_ADDR 0x2
  153. #define SGMII_PHY1_ADDR 0x3
  154. #define SGMII_PHY2_ADDR 0x4
  155. #define FM1_10GEC1_PHY_ADDR 0x0
  156. #define FDT_SEQ_MACADDR_FROM_ENV
  157. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  158. #endif
  159. #endif
  160. /* QSPI device */
  161. #ifndef SPL_NO_QSPI
  162. #ifdef CONFIG_FSL_QSPI
  163. #define CONFIG_SPI_FLASH_SPANSION
  164. #define FSL_QSPI_FLASH_SIZE (1 << 26)
  165. #define FSL_QSPI_FLASH_NUM 2
  166. #endif
  167. #endif
  168. #ifndef SPL_NO_MISC
  169. #undef CONFIG_BOOTCOMMAND
  170. #ifdef CONFIG_TFABOOT
  171. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  172. "env exists secureboot && esbc_halt;;"
  173. #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
  174. "env exists secureboot && esbc_halt;"
  175. #else
  176. #if defined(CONFIG_QSPI_BOOT)
  177. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  178. "env exists secureboot && esbc_halt;;"
  179. #elif defined(CONFIG_SD_BOOT)
  180. #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
  181. "env exists secureboot && esbc_halt;"
  182. #endif
  183. #endif
  184. #endif
  185. #include <asm/fsl_secure_boot.h>
  186. #endif /* __LS1046ARDB_H__ */