ls1046aqds.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1046AQDS_H__
  6. #define __LS1046AQDS_H__
  7. #include "ls1046a_common.h"
  8. #ifndef __ASSEMBLY__
  9. unsigned long get_board_sys_clk(void);
  10. unsigned long get_board_ddr_clk(void);
  11. #endif
  12. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  13. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_LAYERSCAPE_NS_ACCESS
  16. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  17. /* Physical Memory Map */
  18. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  19. #define CONFIG_DDR_SPD
  20. #define SPD_EEPROM_ADDRESS 0x51
  21. #define CONFIG_SYS_SPD_BUS_NUM 0
  22. #define CONFIG_DDR_ECC
  23. #ifdef CONFIG_DDR_ECC
  24. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  25. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  26. #endif
  27. /* DSPI */
  28. #ifdef CONFIG_FSL_DSPI
  29. #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
  30. #define CONFIG_SPI_FLASH_SST /* cs1 */
  31. #define CONFIG_SPI_FLASH_EON /* cs2 */
  32. #endif
  33. /* QSPI */
  34. #if defined(CONFIG_TFABOOT) || \
  35. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  36. #ifdef CONFIG_FSL_QSPI
  37. #define CONFIG_SPI_FLASH_SPANSION
  38. #define FSL_QSPI_FLASH_SIZE (1 << 24)
  39. #define FSL_QSPI_FLASH_NUM 2
  40. #endif
  41. #endif
  42. #ifdef CONFIG_SYS_DPAA_FMAN
  43. #define CONFIG_PHY_VITESSE
  44. #define CONFIG_PHY_REALTEK
  45. #define CONFIG_PHYLIB_10G
  46. #define RGMII_PHY1_ADDR 0x1
  47. #define RGMII_PHY2_ADDR 0x2
  48. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  49. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  50. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  51. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  52. /* PHY address on QSGMII riser card on slot 2 */
  53. #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  54. #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  55. #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  56. #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  57. #endif
  58. #ifdef CONFIG_RAMBOOT_PBL
  59. #define CONFIG_SYS_FSL_PBL_PBI \
  60. board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  61. #endif
  62. #ifdef CONFIG_NAND_BOOT
  63. #define CONFIG_SYS_FSL_PBL_RCW \
  64. board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  65. #endif
  66. #ifdef CONFIG_SD_BOOT
  67. #ifdef CONFIG_SD_BOOT_QSPI
  68. #define CONFIG_SYS_FSL_PBL_RCW \
  69. board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  70. #else
  71. #define CONFIG_SYS_FSL_PBL_RCW \
  72. board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  73. #endif
  74. #endif
  75. /* IFC */
  76. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  77. #define CONFIG_FSL_IFC
  78. /*
  79. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  80. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  81. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  82. * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  83. */
  84. #define CONFIG_SYS_FLASH_BASE 0x60000000
  85. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  86. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  87. #ifdef CONFIG_MTD_NOR_FLASH
  88. #define CONFIG_SYS_FLASH_QUIET_TEST
  89. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  90. #endif
  91. #endif
  92. /* LPUART */
  93. #ifdef CONFIG_LPUART
  94. #define CONFIG_LPUART_32B_REG
  95. #define CFG_UART_MUX_MASK 0x6
  96. #define CFG_UART_MUX_SHIFT 1
  97. #define CFG_LPUART_EN 0x2
  98. #endif
  99. /* EEPROM */
  100. #define CONFIG_ID_EEPROM
  101. #define CONFIG_SYS_I2C_EEPROM_NXID
  102. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  103. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  104. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  105. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  106. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  107. /*
  108. * IFC Definitions
  109. */
  110. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  111. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  112. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  113. CSPR_PORT_SIZE_16 | \
  114. CSPR_MSEL_NOR | \
  115. CSPR_V)
  116. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  117. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  118. + 0x8000000) | \
  119. CSPR_PORT_SIZE_16 | \
  120. CSPR_MSEL_NOR | \
  121. CSPR_V)
  122. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  123. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  124. CSOR_NOR_TRHZ_80)
  125. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  126. FTIM0_NOR_TEADC(0x5) | \
  127. FTIM0_NOR_TAVDS(0x6) | \
  128. FTIM0_NOR_TEAHC(0x5))
  129. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  130. FTIM1_NOR_TRAD_NOR(0x1a) | \
  131. FTIM1_NOR_TSEQRAD_NOR(0x13))
  132. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
  133. FTIM2_NOR_TCH(0x8) | \
  134. FTIM2_NOR_TWPH(0xe) | \
  135. FTIM2_NOR_TWP(0x1c))
  136. #define CONFIG_SYS_NOR_FTIM3 0
  137. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  138. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  139. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  140. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  141. #define CONFIG_SYS_FLASH_EMPTY_INFO
  142. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  143. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  144. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  145. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  146. /*
  147. * NAND Flash Definitions
  148. */
  149. #define CONFIG_NAND_FSL_IFC
  150. #define CONFIG_SYS_NAND_BASE 0x7e800000
  151. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  152. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  153. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  154. | CSPR_PORT_SIZE_8 \
  155. | CSPR_MSEL_NAND \
  156. | CSPR_V)
  157. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  158. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  159. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  160. | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
  161. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  162. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  163. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  164. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  165. #define CONFIG_SYS_NAND_ONFI_DETECTION
  166. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  167. FTIM0_NAND_TWP(0x18) | \
  168. FTIM0_NAND_TWCHT(0x7) | \
  169. FTIM0_NAND_TWH(0xa))
  170. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  171. FTIM1_NAND_TWBE(0x39) | \
  172. FTIM1_NAND_TRR(0xe) | \
  173. FTIM1_NAND_TRP(0x18))
  174. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  175. FTIM2_NAND_TREH(0xa) | \
  176. FTIM2_NAND_TWHRE(0x1e))
  177. #define CONFIG_SYS_NAND_FTIM3 0x0
  178. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  179. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  180. #define CONFIG_MTD_NAND_VERIFY_WRITE
  181. #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
  182. #endif
  183. #ifdef CONFIG_NAND_BOOT
  184. #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
  185. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  186. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  187. #endif
  188. #if defined(CONFIG_TFABOOT) || \
  189. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  190. #define CONFIG_QIXIS_I2C_ACCESS
  191. #define CONFIG_SYS_I2C_EARLY_INIT
  192. #endif
  193. /*
  194. * QIXIS Definitions
  195. */
  196. #define CONFIG_FSL_QIXIS
  197. #ifdef CONFIG_FSL_QIXIS
  198. #define QIXIS_BASE 0x7fb00000
  199. #define QIXIS_BASE_PHYS QIXIS_BASE
  200. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  201. #define QIXIS_LBMAP_SWITCH 6
  202. #define QIXIS_LBMAP_MASK 0x0f
  203. #define QIXIS_LBMAP_SHIFT 0
  204. #define QIXIS_LBMAP_DFLTBANK 0x00
  205. #define QIXIS_LBMAP_ALTBANK 0x04
  206. #define QIXIS_LBMAP_NAND 0x09
  207. #define QIXIS_LBMAP_SD 0x00
  208. #define QIXIS_LBMAP_SD_QSPI 0xff
  209. #define QIXIS_LBMAP_QSPI 0xff
  210. #define QIXIS_RCW_SRC_NAND 0x110
  211. #define QIXIS_RCW_SRC_SD 0x040
  212. #define QIXIS_RCW_SRC_QSPI 0x045
  213. #define QIXIS_RST_CTL_RESET 0x41
  214. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  215. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  216. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  217. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  218. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  219. CSPR_PORT_SIZE_8 | \
  220. CSPR_MSEL_GPCM | \
  221. CSPR_V)
  222. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  223. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  224. CSOR_NOR_NOR_MODE_AVD_NOR | \
  225. CSOR_NOR_TRHZ_80)
  226. /*
  227. * QIXIS Timing parameters for IFC GPCM
  228. */
  229. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
  230. FTIM0_GPCM_TEADC(0x20) | \
  231. FTIM0_GPCM_TEAHC(0x10))
  232. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
  233. FTIM1_GPCM_TRAD(0x1f))
  234. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
  235. FTIM2_GPCM_TCH(0x8) | \
  236. FTIM2_GPCM_TWP(0xf0))
  237. #define CONFIG_SYS_FPGA_FTIM3 0x0
  238. #endif
  239. #ifdef CONFIG_TFABOOT
  240. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  241. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  242. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  243. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  244. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  245. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  246. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  247. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  248. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  249. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  250. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  251. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  252. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  253. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  254. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  255. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  256. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  257. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  258. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  259. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  260. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  261. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  262. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  263. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  264. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  265. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  266. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  267. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  268. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  269. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  270. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  271. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  272. #else
  273. #ifdef CONFIG_NAND_BOOT
  274. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  275. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  276. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  277. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  278. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  279. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  280. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  281. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  282. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  283. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  284. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  285. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  286. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  287. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  288. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  289. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  290. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  291. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  292. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  293. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  294. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  295. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  296. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  297. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  298. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  299. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  300. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  301. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  302. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  303. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  304. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  305. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  306. #else
  307. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  308. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  309. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  310. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  311. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  312. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  313. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  314. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  315. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  316. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  317. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  318. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  319. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  320. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  321. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  322. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  323. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  324. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  325. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  326. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  327. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  328. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  329. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  330. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  331. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  332. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  333. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  334. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  335. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  336. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  337. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  338. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  339. #endif
  340. #endif
  341. /*
  342. * I2C bus multiplexer
  343. */
  344. #define I2C_MUX_PCA_ADDR_PRI 0x77
  345. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  346. #define I2C_RETIMER_ADDR 0x18
  347. #define I2C_MUX_CH_DEFAULT 0x8
  348. #define I2C_MUX_CH_CH7301 0xC
  349. #define I2C_MUX_CH5 0xD
  350. #define I2C_MUX_CH6 0xE
  351. #define I2C_MUX_CH7 0xF
  352. #define I2C_MUX_CH_VOL_MONITOR 0xa
  353. /* Voltage monitor on channel 2*/
  354. #define I2C_VOL_MONITOR_ADDR 0x40
  355. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  356. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  357. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  358. #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
  359. #ifndef CONFIG_SPL_BUILD
  360. #define CONFIG_VID
  361. #endif
  362. #define CONFIG_VOL_MONITOR_IR36021_SET
  363. #define CONFIG_VOL_MONITOR_INA220
  364. /* The lowest and highest voltage allowed for LS1046AQDS */
  365. #define VDD_MV_MIN 819
  366. #define VDD_MV_MAX 1212
  367. /*
  368. * Miscellaneous configurable options
  369. */
  370. #define CONFIG_SYS_MEMTEST_START 0x80000000
  371. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  372. #define CONFIG_SYS_HZ 1000
  373. #define CONFIG_SYS_INIT_SP_OFFSET \
  374. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  375. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  376. /*
  377. * Environment
  378. */
  379. #define CONFIG_ENV_OVERWRITE
  380. #ifdef CONFIG_TFABOOT
  381. #define CONFIG_SYS_MMC_ENV_DEV 0
  382. #else
  383. #ifdef CONFIG_NAND_BOOT
  384. #elif defined(CONFIG_SD_BOOT)
  385. #define CONFIG_SYS_MMC_ENV_DEV 0
  386. #endif
  387. #endif
  388. #define CONFIG_CMDLINE_TAG
  389. #undef CONFIG_BOOTCOMMAND
  390. #ifdef CONFIG_TFABOOT
  391. #define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \
  392. "e0000 f00000 && bootm $kernel_load"
  393. #define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
  394. "$kernel_size && bootm $kernel_load"
  395. #define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \
  396. "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
  397. #else
  398. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  399. #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
  400. "e0000 f00000 && bootm $kernel_load"
  401. #else
  402. #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
  403. "$kernel_size && bootm $kernel_load"
  404. #endif
  405. #endif
  406. #include <asm/fsl_secure_boot.h>
  407. #endif /* __LS1046AQDS_H__ */