ls1046afrwy.h 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #ifndef __LS1046AFRWY_H__
  6. #define __LS1046AFRWY_H__
  7. #include "ls1046a_common.h"
  8. #define CONFIG_SYS_CLK_FREQ 100000000
  9. #define CONFIG_DDR_CLK_FREQ 100000000
  10. #define CONFIG_LAYERSCAPE_NS_ACCESS
  11. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  12. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  13. #define CONFIG_SYS_UBOOT_BASE 0x40100000
  14. /* IFC */
  15. #define CONFIG_FSL_IFC
  16. /*
  17. * NAND Flash Definitions
  18. */
  19. #define CONFIG_NAND_FSL_IFC
  20. #define CONFIG_SYS_NAND_BASE 0x7e800000
  21. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  22. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  23. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  24. | CSPR_PORT_SIZE_8 \
  25. | CSPR_MSEL_NAND \
  26. | CSPR_V)
  27. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  28. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  29. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  30. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  31. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  32. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  33. | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
  34. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  35. #define CONFIG_SYS_NAND_ONFI_DETECTION
  36. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  37. FTIM0_NAND_TWP(0x18) | \
  38. FTIM0_NAND_TWCHT(0x7) | \
  39. FTIM0_NAND_TWH(0xa))
  40. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  41. FTIM1_NAND_TWBE(0x39) | \
  42. FTIM1_NAND_TRR(0xe) | \
  43. FTIM1_NAND_TRP(0x18))
  44. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  45. FTIM2_NAND_TREH(0xa) | \
  46. FTIM2_NAND_TWHRE(0x1e))
  47. #define CONFIG_SYS_NAND_FTIM3 0x0
  48. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  49. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  50. #define CONFIG_MTD_NAND_VERIFY_WRITE
  51. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  52. /* IFC Timing Params */
  53. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  54. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  55. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  56. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  57. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  58. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  59. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  60. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  61. /* EEPROM */
  62. #define CONFIG_ID_EEPROM
  63. #define CONFIG_SYS_I2C_EEPROM_NXID
  64. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  65. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  66. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  67. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  68. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  69. #define I2C_RETIMER_ADDR 0x18
  70. /* I2C bus multiplexer */
  71. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  72. #define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
  73. #define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
  74. /* RTC */
  75. #define RTC
  76. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
  77. #define CONFIG_SYS_RTC_BUS_NUM 0
  78. /*
  79. * Environment
  80. */
  81. #define CONFIG_ENV_OVERWRITE
  82. #define CONFIG_SYS_MMC_ENV_DEV 0
  83. #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
  84. /* FMan */
  85. #ifdef CONFIG_SYS_DPAA_FMAN
  86. #define CONFIG_FMAN_ENET
  87. #define QSGMII_PORT1_PHY_ADDR 0x1c
  88. #define QSGMII_PORT2_PHY_ADDR 0x1d
  89. #define QSGMII_PORT3_PHY_ADDR 0x1e
  90. #define QSGMII_PORT4_PHY_ADDR 0x1f
  91. #define FDT_SEQ_MACADDR_FROM_ENV
  92. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  93. #endif
  94. /* QSPI device */
  95. #ifdef CONFIG_FSL_QSPI
  96. #define FSL_QSPI_FLASH_SIZE SZ_64M
  97. #define FSL_QSPI_FLASH_NUM 1
  98. #endif
  99. #undef CONFIG_BOOTCOMMAND
  100. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  101. "env exists secureboot && esbc_halt;;"
  102. #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
  103. "env exists secureboot && esbc_halt;"
  104. #include <asm/fsl_secure_boot.h>
  105. #endif /* __LS1046AFRWY_H__ */